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1. 发明授权

US07797665B1 Patterns for routing nets in a programmable logic device 有权
标题翻译：用于在可编程逻辑器件中路由网络的模式
公开(公告)号：US07797665B1
公开(公告)日：2010-09-14
申请号：US11999559
申请日：2007-12-06
申请人： Hui Xu , Vinay Verma , Anirban Rahut , Jason H. Anderson , Sandor S. Kalman
发明人： Hui Xu , Vinay Verma , Anirban Rahut , Jason H. Anderson , Sandor S. Kalman
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Nets of a logic design are efficiently routed in a programmable logic device, which includes multiple types of programmable interconnects. Patterns are read from a library in a storage device. Each pattern includes an ordered set of the types of the programmable interconnects. A path is determined from the source to the destination for each net of the logic design. The path is through a sequence of the programmable interconnects having types that correspond to each type in the ordered set of a selected pattern. A description is output of the path for each of the nets.
摘要翻译：逻辑设计的网络可编程逻辑器件有效路由，可编程逻辑器件包括多种类型的可编程互连。从存储设备中的库中读取模式。每个模式包括可编程互连类型的有序集合。对于逻辑设计的每个网络，从源到目的地确定路径。该路径通过可编程互连序列，其具有对应于所选模式的有序集合中的每种类型的类型。描述是每个网络的路径的输出。

2. 发明授权

US07725868B1 Method and apparatus for facilitating signal routing within a programmable logic device 有权
标题翻译：用于促进可编程逻辑器件内的信号路由的方法和装置
公开(公告)号：US07725868B1
公开(公告)日：2010-05-25
申请号：US11983550
申请日：2007-11-09
申请人： Vinay Verma , Anirban Rahut , Sudip K. Nag , Jason H. Anderson , Rajeev Jayaraman
发明人： Vinay Verma , Anirban Rahut , Sudip K. Nag , Jason H. Anderson , Rajeev Jayaraman
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： H01L27/0207 , G06F17/5027 , G06F17/5077 , H01L27/11803
摘要： Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for each of the groups, the routing resources are of a same type. Pairs of the groups are related by an association of at least one routing resource in one group of a pair of groups capable of being electrically connected to at least one other routing resource in another group of the pair of groups.
摘要翻译：描述了在具有路由资源的可编程逻辑设备内促进信号路由的方法和装置。在一个示例中，路由资源被形成为其中对于每个组的路由资源是相同类型的组。这些组中的一组通过能够与一对组的另一组中的至少一个其他路由资源电连接的一组组中的至少一个路由资源的关联相关联。

3. 发明授权

US07306977B1 Method and apparatus for facilitating signal routing within a programmable logic device 有权
标题翻译：用于促进可编程逻辑器件内的信号路由的方法和装置
公开(公告)号：US07306977B1
公开(公告)日：2007-12-11
申请号：US10651808
申请日：2003-08-29
申请人： Vinay Verma , Anirban Rahut , Sudip K. Nag , Jason H. Anderson , Rajeev Jayaraman
发明人： Vinay Verma , Anirban Rahut , Sudip K. Nag , Jason H. Anderson , Rajeev Jayaraman
IPC分类号： H01L21/82
CPC分类号： H01L27/0207 , G06F17/5027 , G06F17/5077 , H01L27/11803
摘要： Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for each of the groups, the routing resources are of a same type. Pairs of the groups are related by an association of at least one routing resource in one group of a pair of groups capable of being electrically connected to at least one other routing resource in another group of the pair of groups.
摘要翻译：描述了在具有路由资源的可编程逻辑设备内促进信号路由的方法和装置。在一个示例中，路由资源被形成为其中对于每个组的路由资源是相同类型的组。这些组中的一组通过能够与一对组的另一组中的至少一个其他路由资源电连接的一组组中的至少一个路由资源的关联相关联。

4. 发明授权

US07620923B1 Run-time efficient methods for routing large multi-fanout nets 有权
标题翻译：运行时高效的路由大型多扇出网络的方法
公开(公告)号：US07620923B1
公开(公告)日：2009-11-17
申请号：US12050452
申请日：2008-03-18
申请人： Raymond Kong , Anirban Rahut
发明人： Raymond Kong , Anirban Rahut
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method of limiting the routing resources of an integrated circuit (IC) that are available for use when routing multi-fanout nets can include selecting a multi-fanout net comprising a source and a plurality of loads and identifying each region of the IC which does not include at least one of the plurality of loads. Each of the regions can have a defined geometry. A type of routing resource can be selected which has a physical orientation with respect to the IC that corresponds to the geometry of the regions of the IC. Each routing resource of the selected type that is located within a region of the IC which does not include at least one of the plurality of loads can be excluded from consideration when routing the multi-fanout net.
摘要翻译：限制可用于路由多扇出网络的集成电路（IC）的路由资源的方法可以包括选择包括源和多个负载的多扇出网络，并且识别IC的每个区域不包括多个负载中的至少一个。每个区域可以具有限定的几何形状。可以选择一种类型的路由资源，其具有相对于IC的物理取向，其对应于IC的区域的几何形状。当路由多扇出网时，可以排除位于IC区域内不包括多个负载中的至少一个的所选类型的每个路由资源。

5. 发明授权

US07424697B1 Assigning inputs of look-up tables to improve a design implementation in a programmable logic device 有权
标题翻译：分配查询表的输入以改善可编程逻辑器件中的设计实现
公开(公告)号：US07424697B1
公开(公告)日：2008-09-09
申请号：US11707317
申请日：2007-02-16
申请人： Hasan Arslan , Anirban Rahut
发明人： Hasan Arslan , Anirban Rahut
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5031 , G06F2217/84
摘要： Methods for improving an implementation of a design in a programmable logic device (PLD). A topological level of the design implementation is determined for each look-up table (LUT) of the PLD. A subset of the LUTs that are on the critical timing paths of the design implementation is determined. For each LUT in the subset at each topological level, a set combinations is determined for assigning signals to the inputs of the LUT. A current assignment of the signals to the LUT inputs is initialized according to the design implementation. For each LUT in the subset at each topological level, the method determines whether a respective assignment for each combination in the set for the LUT improves a timing metric for the LUT relative to the current assignment for the LUT, and the current assignment is updated when the respective assignment improves the timing metric for the LUT.
摘要翻译：用于改进可编程逻辑器件（PLD）中的设计的实现的方法。为PLD的每个查找表（LUT）确定设计实现的拓扑级别。确定在设计实现的关键定时路径上的LUT的子集。对于每个拓扑级别的子集中的每个LUT，确定用于将信号分配给LUT的输入的集合组合。根据设计实现初始化对LUT输入的信号的当前分配。对于每个拓扑级别的子集中的每个LUT，该方法确定用于LUT的集合中的每个组合的相应分配是否相对于LUT的当前分配改进了LUT的定时度量，并且当相应的分配改进了LUT的定时度量。

6. 发明授权

US07051312B1 Upper-bound calculation for placed circuit design performance 有权
标题翻译：放置电路设计性能的上限计算
公开(公告)号：US07051312B1
公开(公告)日：2006-05-23
申请号：US10603219
申请日：2003-06-24
申请人： Anirban Rahut , Sudip K. Nag
发明人： Anirban Rahut , Sudip K. Nag
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/62
摘要： Within a computer automated tool, a method (400) of estimating an upper-bound of an operational frequency of at least a portion of a placed circuit design can include identifying (405) a clock source within the placed circuit design, wherein the clock source is associated with a clock domain, and determining (410) an initial routing of the clock domain. The method also can include determining (420) a minimum path slack corresponding to each connection of the clock domain. Connections of the clock domain which have a lowest minimum path slack can be marked (430). One or more marked connections which are not routed in delay mode can be identified and routed in delay mode (455) allowing sharing of routing resources by different nets.
摘要翻译：在计算机自动化工具中，估计放置的电路设计的至少一部分的工作频率的上限的方法（400）可以包括在放置的电路设计内识别（405）时钟源，其中时钟源与时钟域相关联，并且确定（410）时钟域的初始路由。该方法还可以包括确定（420）对应于时钟域的每个连接的最小路径松弛。可以标记具有最低最小路径松弛的时钟域的连接（430）。在延迟模式下不被路由的一个或多个标记连接可以以延迟模式（455）被识别和路由，从而允许不同网络共享路由资源。

7. 发明授权

US07430728B1 Method and apparatus for selecting programmable interconnects to reduce clock skew 有权
标题翻译：用于选择可编程互连以减少时钟偏移的方法和装置
公开(公告)号：US07430728B1
公开(公告)日：2008-09-30
申请号：US11200686
申请日：2005-08-10
申请人： Anirban Rahut
发明人： Anirban Rahut
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/62
摘要： A method and apparatus for selecting programmable interconnects to reduce clock skew is described. A routing tree for clock signals is created having routes and clock pin nodes. Delays of the clock signals to the clock pin nodes are determined. The routing tree is balanced to a target clock skew, such as zero clock skew, for the clock signals provided to the clock pin nodes. Programmable interconnect circuits are selectively added to reduce clock skews of the clock signals, where the clock skews being reduced at the clock pin nodes are for at least a portion of the clock pin nodes. Additionally described are determining clock propagation delays to clock pins and balancing a clock tree using computer aided design.
摘要翻译：描述了一种用于选择可编程互连以减少时钟偏差的方法和装置。创建时钟信号的路由树，具有路由和时钟引脚节点。确定时钟引脚节点的时钟信号延迟。对于提供给时钟引脚节点的时钟信号，路由树被平衡到目标时钟偏移，例如零时钟偏移。选择性地添加可编程互连电路以减少时钟信号的时钟偏差，其中在时钟引脚节点减少的时钟偏差用于时钟引脚节点的至少一部分。另外描述的是确定时钟引脚的时钟传播延迟和使用计算机辅助设计平衡时钟树。

8. 发明授权

US06952813B1 Method and apparatus for selecting programmable interconnects to reduce clock skew 有权
标题翻译：用于选择可编程互连以减少时钟偏移的方法和装置
公开(公告)号：US06952813B1
公开(公告)日：2005-10-04
申请号：US10631564
申请日：2003-07-30
申请人： Anirban Rahut
发明人： Anirban Rahut
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/62
摘要： A method and apparatus for selecting programmable interconnects to reduce clock skew is described. A routing tree for clock signals is created having routes and clock pin nodes. Delays of the clock signals to the clock pin nodes are determined. The routing tree is balanced to a target clock skew, such as zero clock skew, for the clock signals provided to the clock pin nodes. Programmable interconnect circuits are selectively added to reduce clock skews of the clock signals, where the clock skews being reduced at the clock pin nodes are for at least a portion of the clock pin nodes. Additionally described are determining clock propagation delays to clock pins and balancing a clock tree using computer aided design.
摘要翻译：描述了一种用于选择可编程互连以减少时钟偏差的方法和装置。创建时钟信号的路由树，具有路由和时钟引脚节点。确定时钟引脚节点的时钟信号延迟。对于提供给时钟引脚节点的时钟信号，路由树被平衡到目标时钟偏移，例如零时钟偏移。选择性地添加可编程互连电路以减少时钟信号的时钟偏差，其中在时钟引脚节点减少的时钟偏差用于时钟引脚节点的至少一部分。另外描述的是确定时钟引脚的时钟传播延迟和使用计算机辅助设计平衡时钟树。

9. 发明授权

US07904860B1 Method and apparatus for selecting programmable interconnects to reduce clock skew 有权
标题翻译：用于选择可编程互连以减少时钟偏移的方法和装置
公开(公告)号：US07904860B1
公开(公告)日：2011-03-08
申请号：US12194403
申请日：2008-08-19
申请人： Anirban Rahut
发明人： Anirban Rahut
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/62
摘要： A method and apparatus for selecting programmable interconnects to reduce clock skew is described. A routing tree for clock signals is created having routes and clock pin nodes. Delays of the clock signals to the clock pin nodes are determined. The routing tree is balanced to a target clock skew, such as zero clock skew, for the clock signals provided to the clock pin nodes. Programmable interconnect circuits are selectively added to reduce clock skews of the clock signals, where the clock skews being reduced at the clock pin nodes are for at least a portion of the clock pin nodes. Additionally described are determining clock propagation delays to clock pins and balancing a clock tree using computer aided design.
摘要翻译：描述了一种用于选择可编程互连以减少时钟偏差的方法和装置。创建时钟信号的路由树，具有路由和时钟引脚节点。确定时钟引脚节点的时钟信号延迟。对于提供给时钟引脚节点的时钟信号，路由树被平衡到目标时钟偏移，例如零时钟偏移。选择性地添加可编程互连电路以减少时钟信号的时钟偏差，其中在时钟引脚节点减少的时钟偏差用于时钟引脚节点的至少一部分。另外描述的是确定时钟引脚的时钟传播延迟和使用计算机辅助设计平衡时钟树。

10. 发明授权

US07735039B1 Methods of estimating net delays in tile-based PLD architectures 有权
标题翻译：估计基于瓦片的PLD架构的网络延迟的方法
公开(公告)号：US07735039B1
公开(公告)日：2010-06-08
申请号：US11895899
申请日：2007-08-28
申请人： Srinivasan Dasasathyan , Hasan Arslan , Meng Lou , Anirban Rahut
发明人： Srinivasan Dasasathyan , Hasan Arslan , Meng Lou , Anirban Rahut
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5054 , G06F2217/84
摘要： Methods of estimating delays between pins on a tile-based programmable logic device (PLD), by identifying repeat patterns and exploiting these patterns to provide accurate delay estimates. A computer-implemented method can include selecting a sample area in a tile-based PLD and constructing a delay table corresponding to the sample area. Each entry in the delay table includes a base delay value and a description of the fastest available route from a source pin in a source tile to a load pin in the sample area. To estimate a net delay, the base delay value and the description of the route are read from the delay table for specified source and load pins. One or more delay variants (e.g., pin delays and/or crossing penalties) are calculated based on the description of the route. The calculated delay variants are added to the base delay value to obtain an adjusted delay value, which is output.
摘要翻译：通过识别重复模式并利用这些模式来提供准确的延迟估计来估计基于瓦片的可编程逻辑器件（PLD）的引脚之间的延迟的方法。计算机实现的方法可以包括在基于瓦片的PLD中选择样本区域并构建对应于样本区域的延迟表。延迟表中的每个条目包括基本延迟值以及从源块中的源引脚到采样区中的负载引脚的最快可用路由的描述。为了估计净延迟，从延迟表中读取指定的源和负载引脚的基本延迟值和路由的描述。基于路线的描述来计算一个或多个延迟变型（例如，引脚延迟和/或交叉惩罚）。将计算的延迟变量加到基本延迟值中，以获得输出的经调整的延迟值。

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