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1. 发明授权

US08015535B1 Run-time efficient methods for routing large multi-fanout nets 有权
标题翻译：运行时高效的路由大型多扇出网络的方法
公开(公告)号：US08015535B1
公开(公告)日：2011-09-06
申请号：US12050447
申请日：2008-03-18
申请人： Raymond Kong , Anirban Rahut
发明人： Raymond Kong , Anirban Rahut
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method of limiting the routing resources of an integrated circuit (IC) that are available for use when routing multi-fanout nets can include selecting a multi-fanout net comprising a source and a plurality of loads and identifying each region of the IC which does not include at least one of the plurality of loads. Each of the regions can have a defined geometry. A type of routing resource can be selected which has a physical orientation with respect to the IC that corresponds to the geometry of the regions of the IC. Each routing resource of the selected type that is located within a region of the IC which does not include at least one of the plurality of loads can be excluded from consideration when routing the multi-fanout net.
摘要翻译：限制可用于路由多扇出网络的集成电路（IC）的路由资源的方法可以包括选择包括源和多个负载的多扇出网络，并且识别IC的每个区域不包括多个负载中的至少一个。每个区域可以具有限定的几何形状。可以选择一种类型的路由资源，其具有相对于IC的物理取向，其对应于IC的区域的几何形状。当路由多扇出网时，可以排除位于IC区域内不包括多个负载中的至少一个的所选类型的每个路由资源。

2. 发明授权

US07590960B1 Placing partitioned circuit designs within iterative implementation flows 有权
标题翻译：将分隔电路设计放在迭代实现流程中
公开(公告)号：US07590960B1
公开(公告)日：2009-09-15
申请号：US11787925
申请日：2007-04-18
申请人： Raymond Kong , Navaratnasothie Selvakkumaran , Kamal Chaudhary
发明人： Raymond Kong , Navaratnasothie Selvakkumaran , Kamal Chaudhary
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5072
摘要： A method of placing circuit elements of a partitioned circuit design on a target programmable logic device (PLD) can include mapping circuit elements of the circuit design to corresponding partitions of the circuit design, selecting a circuit element of the circuit design, and selecting a candidate location within a logic boundary on the target PLD. The method also can include validating the candidate location for the selected circuit element, at least in part, according to whether the selected circuit element belongs to a same partition of the circuit design as at least one other circuit element already placed within the logic boundary. The selected circuit element can be selectively placed at the candidate location according to the validation.
摘要翻译：将分割电路设计的电路元件放置在目标可编程逻辑器件（PLD）上的方法可以包括将电路设计的电路元件映射到电路设计的相应分区，选择电路设计的电路元件，以及选择候选位于目标PLD的逻辑边界内。该方法还可以包括至少部分地根据所选择的电路元件是否属于与已经放置在逻辑边界内的至少一个其它电路元件的电路设计的相同分区来验证所选择的电路元件的候选位置。所选择的电路元件可以根据验证选择性地放置在候选位置。

3. 发明授权

US07524472B1 Mercury removal from coal emissions using montmorillonite clay 失效
标题翻译：使用蒙脱石粘土从煤炭排放中去除汞
公开(公告)号：US07524472B1
公开(公告)日：2009-04-28
申请号：US11600700
申请日：2006-11-15
申请人： Raymond Kong
发明人： Raymond Kong
IPC分类号： B01D53/64 , B01J20/12 , C09K3/00
CPC分类号： B01D53/64 , B01D53/77 , B01D2251/10 , B01D2253/11 , B01D2257/602 , B01D2259/40 , B01J20/12 , F23J15/006 , F23J2215/60 , F23J2219/60
摘要： Disclosed herein are methods, apparatus, and compositions for removing mercury gas from coal combustion emissions and the like. Disclosed herein is a gettering composition comprising an activated montmorillonite clay, a method for removing mercury from a gas stream using the gettering composition, and an apparatus for removing mercury from a gas stream.
摘要翻译：本文公开了用于从煤燃烧排放物等中去除汞气体的方法，装置和组合物。本文公开了包含活性蒙脱石粘土的吸气组合物，使用吸气组合物从气流中除去汞的方法，以及从气流中除去汞的装置。

4. 发明授权

US08141010B1 Method and arrangement providing for implementation granularity using implementation sets 有权
公开(公告)号：US08141010B1
公开(公告)日：2012-03-20
申请号：US12028337
申请日：2008-02-08
申请人： Raymond Kong , Daniel J. Downs , John J. Laurence , Richard Yachyang Sun , Sankaranarayanan Srinivasan
发明人： Raymond Kong , Daniel J. Downs , John J. Laurence , Richard Yachyang Sun , Sankaranarayanan Srinivasan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.

5. 发明授权

US07290241B1 Method and system for managing behavior of algorithms 有权
标题翻译：用于管理算法行为的方法和系统
公开(公告)号：US07290241B1
公开(公告)日：2007-10-30
申请号：US10913752
申请日：2004-08-06
申请人： Daniel J. Downs , John D. Bunte , Raymond Kong , John J. Laurence , Richard Yachyang Sun
发明人： Daniel J. Downs , John D. Bunte , Raymond Kong , John J. Laurence , Richard Yachyang Sun
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of managing behavior of algorithms includes specifying governing rules/policies that manage I-Set implementation directives, command line options, and environment variables and loading governing rules/policies into a behavior manager. Inside a client tool, the I-Set hierarchy processes and iterates one I-Set node at a time. Without more I-Sets to process, the method is done. If more, then the tool queries the Behavior Manager with an I-Set with symbolic designators of the queried behavior. The Behavior Manager can reply to the client tool indicating whether the queried behavior is to be supported on the appropriate logic of the I-Set node. If the algorithm for the I-Set node lacks the queried behavior, then another I-Set might require processing. If the algorithm for the I-Set node has the queried behavior, then the client tool applies the corresponding algorithm(s) on the appropriate logic.
摘要翻译：一种管理算法行为的方法包括指定管理I-Set实现指令，命令行选项和环境变量的管理规则/策略，并将管理规则/策略加载到行为管理器中。在客户端工具中，I-Set层次结构一次处理并迭代一个I-Set节点。没有更多的I-Sets要处理，该方法就完成了。如果更多，那么该工具将使用具有查询行为的符号指示符的I-Set查询“行为管理器”。行为管理器可以回复客户端工具，指示是否在I-Set节点的相应逻辑上支持查询行为。如果I-Set节点的算法缺少查询行为，则另一个I-Set可能需要处理。如果I-Set节点的算法具有查询行为，则客户端工具将相应的算法应用于适当的逻辑。

6. 发明授权

US06732347B1 Clock template for configuring a programmable gate array 有权
标题翻译：用于配置可编程门阵列的时钟模板
公开(公告)号：US06732347B1
公开(公告)日：2004-05-04
申请号：US09844054
申请日：2001-04-26
申请人： Nicolas J. Camilleri , Edward S. McGettigan , Kenneth J. Stickney, Jr. , Jeffrey V. Lindholm , Kevin L. Bixler , Raymond Kong
发明人： Nicolas J. Camilleri , Edward S. McGettigan , Kenneth J. Stickney, Jr. , Jeffrey V. Lindholm , Kevin L. Bixler , Raymond Kong
IPC分类号： G06F1750
CPC分类号： G06F1/10 , G06F17/5054
摘要： A clock template includes digital programming information for programming clock frames of a programmable gate array (PGA). The digital programming information represents a number of different clock configurations that correspond to various designs in the PGA. In one embodiment, the digital programming information includes a bit stream for partially reconfiguring the PGA. In another embodiment, the digital programming information is embedded in digital programming information of at least one of the designs. Methods of configuring a PGA with different designs having different clocking configurations by utilizing the clock template are also disclosed.
摘要翻译：时钟模板包括用于编程可编程门阵列（PGA）的时钟帧的数字编程信息。数字编程信息表示与PGA中的各种设计相对应的多种不同的时钟配置。在一个实施例中，数字节目信息包括用于部分重新配置PGA的比特流。在另一个实施例中，数字节目信息被嵌入至少一个设计的数字节目信息中。还公开了通过利用时钟模板来配置具有不同时钟配置的不同设计的PGA的方法。

7. 发明授权

US08549454B1 System and method for automated configuration of design constraints 有权
标题翻译：用于自动配置设计约束的系统和方法
公开(公告)号：US08549454B1
公开(公告)日：2013-10-01
申请号：US13554418
申请日：2012-07-20
申请人： Raymond Kong , David A. Knol , Frederic Revenu , Dinesh K. Monga
发明人： Raymond Kong , David A. Knol , Frederic Revenu , Dinesh K. Monga
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/06
摘要： In one embodiment, a method for propagating design constraints between a module and a module instance in a circuit design is provided. A port of the module and a port/pin of the circuit design are determined, between which constraints are to be propagated. The determination of the port/pin includes determining whether or not pin of the module instance corresponding to the port is directly connected to a top-level port of the circuit design. In response to determining that the pin is directly connected to a top-level port, the top-level port is selected as the port/pin. In response to determining that the pin is not directly connected to the top-level port, the pin is selected as the port/pin. Design constraints are propagated between the port and the selected port/pin. The propagated design constraints are stored in a storage device.
摘要翻译：在一个实施例中，提供了一种用于在电路设计中在模块和模块实例之间传播设计约束的方法。确定模块的端口和电路设计的端口/引脚，在这些约束之间进行传播。端口/引脚的确定包括确定对应于端口的模块实例的引脚是否直接连接到电路设计的顶级端口。响应于确定引脚直接连接到顶级端口，顶级端口被选择为端口/引脚。响应于确定引脚不直接连接到顶级端口，该引脚被选择为端口/引脚。设计约束在端口和选定端口/引脚之间传播。传播的设计约束存储在存储设备中。

8. 发明授权

US08296690B1 Method and arrangement providing for implementation granularity using implementation sets 有权
标题翻译：使用实现集提供实现粒度的方法和布置
公开(公告)号：US08296690B1
公开(公告)日：2012-10-23
申请号：US12027501
申请日：2008-02-07
申请人： Raymond Kong , Daniel J. Downs , John J. Laurence , Richard Yachyang Sun , Sankaranarayanan Srinivasen
发明人： Raymond Kong , Daniel J. Downs , John J. Laurence , Richard Yachyang Sun , Sankaranarayanan Srinivasen
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.
摘要翻译：基于用于集成电路设计的用户设计的实现集抽象的设计层次结构包括多个节点和多个节点中的每个节点的定义，其描述了包含在每个节点中的元素的类型和所定义的层级通过每个节点。每个节点可以包括设计的至少一个实现元素，并且可以在包括一组逻辑元素，一组放置元素以及一组放置和路由元素的组中选择该至少一个实现元素。

9. 发明授权

US08196083B1 Incremental placement and routing 有权
标题翻译：增量放置和布线
公开(公告)号：US08196083B1
公开(公告)日：2012-06-05
申请号：US12964126
申请日：2010-12-09
申请人： Raymond Kong
发明人： Raymond Kong
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077 , G06F2217/06
摘要： In one embodiment, a method is provided for incremental routing of a circuit design having modified and unmodified signals. Critical routed signals of the partially routed circuit design are determined. For each critical routed signal, a first set of routing constraints is applied to prevent rerouting of the signal. The partially routed circuit design is routed according to the first set of routing constraints to produce a non-conflicting routing solution. In response to the non-conflicting routing solution not meeting timing requirements, the first set of routing constraints is removed and post-routing optimization processes are performed on the non-conflicting routing solution to reduce propagation delay of one or more signals.
摘要翻译：在一个实施例中，提供了一种用于具有修改和未修改信号的电路设计的增量路由选择的方法。确定部分路由电路设计的关键路由信号。对于每个关键的路由信号，应用第一组路由约束来防止信号的重新路由。部分路由电路设计根据第一组路由约束进行路由以产生不冲突的路由解决方案。响应于不符合时序要求的非冲突路由解决方案，去除第一组路由约束，并且在非冲突路由解决方案上执行后路由优化过程以减少一个或多个信号的传播延迟。

10. 发明申请

US20070033582A1 Transforming a Flow Graph Model to a Structured Flow Language Model 失效
标题翻译：将流图模型转换为结构化流语言模型
公开(公告)号：US20070033582A1
公开(公告)日：2007-02-08
申请号：US11161463
申请日：2005-08-04
申请人： Jie Hu , Raymond Kong , Curtis Miles
发明人： Jie Hu , Raymond Kong , Curtis Miles
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/10
摘要： The invention provides a solution for transforming a flow graph model to a structured flow language model. In particular, the nodes in the flow graph model are traversed, and each node is mapped to an activity in the structured flow language model. When a node comprises a branch point, the corresponding branch region is identified and mapped. This process is repeated until all nodes in the flow graph model have been mapped to corresponding activities in the structured flow language model. In this manner, the desired nesting and containment relationships can be identified and generated in the structured flow language model.
摘要翻译：本发明提供了一种用于将流程图模型转换为结构化流程语言模型的解决方案。特别地，遍历流图模型中的节点，并且将每个节点映射到结构化流程语言模型中的活动。当节点包括分支点时，识别并映射相应的分支区域。重复此过程，直到流图模型中的所有节点都已映射到结构化流程语言模型中的相应活动。以这种方式，可以在结构化流程语言模型中识别和生成期望的嵌套和容纳关系。

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