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1. 发明授权

US08250513B1 Parallel process optimized signal routing 有权
标题翻译：并行过程优化信号路由
公开(公告)号：US08250513B1
公开(公告)日：2012-08-21
申请号：US12939765
申请日：2010-11-04
申请人： Vinay Verma , Gitu Jain , Sanjeev Kwatra , Taneem Ahmed , Sandor S. Kalman
发明人： Vinay Verma , Gitu Jain , Sanjeev Kwatra , Taneem Ahmed , Sandor S. Kalman
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5077 , G06F2217/08
摘要： In one embodiment, a method for routing of a circuit design netlist is provided. A processing cost is determined for each net in the netlist. A plurality of regions are defined for the target device such that the total processing costs of nets are balanced between the plurality of regions. Concurrent with routing one or more nets of a first one of the plurality of regions, one or more nets are routed in at least one other of the plurality of regions. Synchronization and subsequent routing are performed for unrouted nets of the netlist.
摘要翻译：在一个实施例中，提供了一种用于路由电路设计网表的方法。网表中的每个网络确定处理成本。为目标设备定义多个区域，使得网络的总处理成本在多个区域之间平衡。与路由多个区域中的第一个区域的一个或多个网络同时，在多个区域中的至少另一个区域中路由一个或多个网络。为网表的未路由网络执行同步和后续路由。

2. 发明授权

US08312409B1 Multi-threaded deterministic router 有权
标题翻译：多线程确定性路由器
公开(公告)号：US08312409B1
公开(公告)日：2012-11-13
申请号：US12718945
申请日：2010-03-05
申请人： Gitu Jain , Vinay Verma , Taneem Ahmed , Sandor S. Kalman , Sanjeev Kwatra , Christopher H. Kingsley , Jason H. Anderson , Satyaki Das
发明人： Gitu Jain , Vinay Verma , Taneem Ahmed , Sandor S. Kalman , Sanjeev Kwatra , Christopher H. Kingsley , Jason H. Anderson , Satyaki Das
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5054
摘要： A method is described that includes: determining that nets of the circuit design comprise overlap, where the overlap indicates that at least two of the nets of the circuit design use a same routing resource; dividing the nets with overlap among a plurality of buckets, where for each bucket, a net of the bucket does not overlap any other net in the bucket; sequentially processing each bucket by unrouting and rerouting, via at least one processor, nets in the bucket; and storing routing information specifying routes for nets of the circuit design.
摘要翻译：描述了一种方法，其包括：确定电路设计的网络包括重叠，其中重叠指示电路设计的网络中的至少两个使用相同的路由资源; 在多个桶之间用重叠划分网，其中对于每个桶，桶的网不与桶中的任何其他网重叠; 通过至少一个处理器，通过在桶中的网络进行路由和重新路由来顺序地处理每个桶; 并存储指定电路设计网络的路由的路由信息。

3. 发明授权

US08201130B1 Parallel signal routing 有权
标题翻译：并行信号路由
公开(公告)号：US08201130B1
公开(公告)日：2012-06-12
申请号：US12939732
申请日：2010-11-04
申请人： Sandor S. Kalman , Vinay Verma , Gitu Jain , Taneem Ahmed , Sanjeev Kwatra
发明人： Sandor S. Kalman , Vinay Verma , Gitu Jain , Taneem Ahmed , Sanjeev Kwatra
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5054
摘要： A method is provided for routing a circuit design netlist. Nets of the netlist are grouped into a plurality of sub-netlists. For each sub-netlist, nets of the sub-netlist are routed as a function of congestion between nets of the sub-netlist. Congestion between nets of other sub-netlists in the plurality of sub-netlists is not taken into account. If two or more nets of the netlist are routed through the same routing resource, a global congestion history data set is updated to describe congestion between all nets in the netlist, and the two or more nets of the netlist are unrouted. The two or more nets are each rerouted as a function of the global congestion history data set and congestion between nets of the same sub-netlist as the net.
摘要翻译：提供了一种用于布线电路设计网表的方法。网表的网络被分组成多个子网表。对于每个子网表，子网表的网络作为子网表的网络之间的拥塞的功能被路由。不考虑多个子网表中其他子网表的网络之间的拥塞。如果网表的两个或多个网络通过相同的路由资源路由，则更新全局拥塞历史数据集，以描述网表中所有网之间的拥塞，并且网表的两个或多个网是未路由的。两个或更多个网络每个被重新路由为全局拥塞历史数据集的功能和与网络相同的子网表的网络之间的拥塞。

4. 发明授权

US08448122B1 Implementing sub-circuits with predictable behavior within a circuit design 有权
标题翻译：在电路设计中实现具有可预测行为的子电路
公开(公告)号：US08448122B1
公开(公告)日：2013-05-21
申请号：US12416326
申请日：2009-04-01
申请人： Vishal Suthar , Hasan Arslan , Sridhar Krishnamurthy , Sanjeev Kwatra , Srinivasan Dasasathyan , Rajat Aggarwal , Sudip K. Nag
发明人： Vishal Suthar , Hasan Arslan , Sridhar Krishnamurthy , Sanjeev Kwatra , Srinivasan Dasasathyan , Rajat Aggarwal , Sudip K. Nag
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of implementing a circuit design within a programmable integrated circuit (IC) can include identifying an implementation directive embedded within a register transfer level (RTL) description of the circuit design and determining components of a sub-circuit of the circuit design, wherein the sub-circuit is specified by a portion of the RTL description associated with the implementation directive. The sub-circuit can be placed for the programmable IC and routed for the programmable IC according to the implementation directive. A programmatic description of the sub-circuit specifying placement and routing information can be output.
摘要翻译：在可编程集成电路（IC）中实现电路设计的方法可以包括识别嵌入在电路设计的寄存器传送电平（RTL）描述内的实现指令并确定电路设计的子电路的组件，其中子电路由与实施指令相关联的RTL描述的一部分指定。可以将子电路放置在可编程IC上，并根据实施指令为可编程IC路由。可以输出指定放置和路由信息的子电路的编程描述。

5. 发明授权

US5617573A State splitting for level reduction 失效
标题翻译：国家分裂降级
公开(公告)号：US5617573A
公开(公告)日：1997-04-01
申请号：US247445
申请日：1994-05-23
申请人： Alan Y. Huang , Steven K. Knapp , Sanjeev Kwatra
发明人： Alan Y. Huang , Steven K. Knapp , Sanjeev Kwatra
IPC分类号： G06F17/50 , G11C13/00
CPC分类号： G06F17/5054
摘要： A method of state splitting in a state machine includes determining a number N of logic levels, i.e. CLB levels, for each state in a state machine. Number N is equal to N.sub.i-1 +log.sub.k f.sub.i wherein "k" is the number of input lines to a CLB, "i" is a particular node in a particular hierarchial level in the Boolean logic, and "f" is the number of fanin transitions to the particular node. An average number N(AV) as well as a maximum number N(MAX) of CLBs to implement the states in the state machine are also determined. Then, predetermined exit criteria are checked. One exit criterion includes determining that the maximum number N(MAX) is not associated with a state register, but is instead associated with an output, for example. Another exit criterion includes providing a ratio by dividing the maximum number N(MAX) by the average number N(AV). If the ratio is less than or equal to a split-factor, then this exit criterion is met. In one embodiment, the split factor is between 1.5 and 2.0. Yet another exit criterion includes determining that the state being analyzed has one or two fanin transitions. If none of the exit criteria are met, then the state associated with the maximum number N(MAX) is split into at least two states. The method is further optimized by repeating all steps until at least one exit criterion is met. State splitting in accordance with the present invention typically reduces the levels of CLBs by approximately 20%, thereby significantly reducing delay in the state machine.
摘要翻译：在状态机中的状态分割的方法包括为状态机中的每个状态确定逻辑电平数目N，即CLB电平。数字N等于Ni-1 + logk fi，其中“k”是到CLB的输入行数，“i”是布尔逻辑中特定层次级别中的特定节点，“f”是 fanin转换到特定节点。还确定了在状态机中实现状态的平均数N（AV）以及最大数目N（MAX）的CLB。然后，检查预定的退出标准。一个退出标准包括确定最大数量N（MAX）不与状态寄存器相关联，而是例如与输出相关联。另一个退出标准包括通过将最大数N（MAX）除以平均数N（AV）来提供比率。如果比率小于或等于分割因子，则满足该退出条件。在一个实施例中，分裂因子在1.5和2.0之间。另一个退出标准包括确定被分析的状态具有一个或两个扇区转换。如果没有符合退出条件，则与最大数N（MAX）相关联的状态被分成至少两个状态。该方法通过重复所有步骤进一步优化，直到满足至少一个退出标准。根据本发明的状态分割通常将CLB的水平降低大约20％，从而显着地减少状态机的延迟。

6. 发明授权

US08122420B1 Congestion elimination using adaptive cost schedule to route signals within an integrated circuit 有权
标题翻译：拥塞消除使用自适应成本计划来路由集成电路内的信号
公开(公告)号：US08122420B1
公开(公告)日：2012-02-21
申请号：US12489302
申请日：2009-06-22
申请人： Parivallal Kannan , Sanjeev Kwatra
发明人： Parivallal Kannan , Sanjeev Kwatra
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A computer-implemented method of routing a circuit design for a target integrated circuit (IC) can include determining a characterization of routing congestion of the circuit design within the target IC and determining a first order cost component of using routing resources of the target IC according to the characterization. The method can include determining a higher order cost component of using routing resources of the target IC according to the characterization and assigning signals of the circuit design to routing resources according to costs calculated using the first order cost component and the higher order cost component. Signal assignments of the circuit design can be output.
摘要翻译：用于路由目标集成电路（IC）的电路设计的计算机实现的方法可以包括确定目标IC内的电路设计的路由拥塞的表征，并且根据目标IC的路由资源确定使用目标IC的路由资源的一阶成本分量表征。该方法可以包括根据表征确定使用目标IC的路由资源的较高阶成本分量，并根据使用第一阶成本分量和较高阶成本分量计算的成本将电路设计的信号分配给路由资源。可以输出电路设计的信号分配。

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