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1. 发明授权

US08312409B1 Multi-threaded deterministic router 有权
标题翻译：多线程确定性路由器
公开(公告)号：US08312409B1
公开(公告)日：2012-11-13
申请号：US12718945
申请日：2010-03-05
申请人： Gitu Jain , Vinay Verma , Taneem Ahmed , Sandor S. Kalman , Sanjeev Kwatra , Christopher H. Kingsley , Jason H. Anderson , Satyaki Das
发明人： Gitu Jain , Vinay Verma , Taneem Ahmed , Sandor S. Kalman , Sanjeev Kwatra , Christopher H. Kingsley , Jason H. Anderson , Satyaki Das
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5054
摘要： A method is described that includes: determining that nets of the circuit design comprise overlap, where the overlap indicates that at least two of the nets of the circuit design use a same routing resource; dividing the nets with overlap among a plurality of buckets, where for each bucket, a net of the bucket does not overlap any other net in the bucket; sequentially processing each bucket by unrouting and rerouting, via at least one processor, nets in the bucket; and storing routing information specifying routes for nets of the circuit design.
摘要翻译：描述了一种方法，其包括：确定电路设计的网络包括重叠，其中重叠指示电路设计的网络中的至少两个使用相同的路由资源; 在多个桶之间用重叠划分网，其中对于每个桶，桶的网不与桶中的任何其他网重叠; 通过至少一个处理器，通过在桶中的网络进行路由和重新路由来顺序地处理每个桶; 并存储指定电路设计网络的路由的路由信息。

2. 发明授权

US08250513B1 Parallel process optimized signal routing 有权
标题翻译：并行过程优化信号路由
公开(公告)号：US08250513B1
公开(公告)日：2012-08-21
申请号：US12939765
申请日：2010-11-04
申请人： Vinay Verma , Gitu Jain , Sanjeev Kwatra , Taneem Ahmed , Sandor S. Kalman
发明人： Vinay Verma , Gitu Jain , Sanjeev Kwatra , Taneem Ahmed , Sandor S. Kalman
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5077 , G06F2217/08
摘要： In one embodiment, a method for routing of a circuit design netlist is provided. A processing cost is determined for each net in the netlist. A plurality of regions are defined for the target device such that the total processing costs of nets are balanced between the plurality of regions. Concurrent with routing one or more nets of a first one of the plurality of regions, one or more nets are routed in at least one other of the plurality of regions. Synchronization and subsequent routing are performed for unrouted nets of the netlist.
摘要翻译：在一个实施例中，提供了一种用于路由电路设计网表的方法。网表中的每个网络确定处理成本。为目标设备定义多个区域，使得网络的总处理成本在多个区域之间平衡。与路由多个区域中的第一个区域的一个或多个网络同时，在多个区域中的至少另一个区域中路由一个或多个网络。为网表的未路由网络执行同步和后续路由。

3. 发明授权

US08201130B1 Parallel signal routing 有权
标题翻译：并行信号路由
公开(公告)号：US08201130B1
公开(公告)日：2012-06-12
申请号：US12939732
申请日：2010-11-04
申请人： Sandor S. Kalman , Vinay Verma , Gitu Jain , Taneem Ahmed , Sanjeev Kwatra
发明人： Sandor S. Kalman , Vinay Verma , Gitu Jain , Taneem Ahmed , Sanjeev Kwatra
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5054
摘要： A method is provided for routing a circuit design netlist. Nets of the netlist are grouped into a plurality of sub-netlists. For each sub-netlist, nets of the sub-netlist are routed as a function of congestion between nets of the sub-netlist. Congestion between nets of other sub-netlists in the plurality of sub-netlists is not taken into account. If two or more nets of the netlist are routed through the same routing resource, a global congestion history data set is updated to describe congestion between all nets in the netlist, and the two or more nets of the netlist are unrouted. The two or more nets are each rerouted as a function of the global congestion history data set and congestion between nets of the same sub-netlist as the net.
摘要翻译：提供了一种用于布线电路设计网表的方法。网表的网络被分组成多个子网表。对于每个子网表，子网表的网络作为子网表的网络之间的拥塞的功能被路由。不考虑多个子网表中其他子网表的网络之间的拥塞。如果网表的两个或多个网络通过相同的路由资源路由，则更新全局拥塞历史数据集，以描述网表中所有网之间的拥塞，并且网表的两个或多个网是未路由的。两个或更多个网络每个被重新路由为全局拥塞历史数据集的功能和与网络相同的子网表的网络之间的拥塞。

4. 发明授权

US06484292B1 Incremental logic synthesis system for revisions of logic circuit designs 有权
标题翻译：用于逻辑电路设计修订的增量逻辑综合系统
公开(公告)号：US06484292B1
公开(公告)日：2002-11-19
申请号：US09499500
申请日：2000-02-07
申请人： Gitu Jain , Soren T. Soe
发明人： Gitu Jain , Soren T. Soe
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： A method and apparatus for implementing incremental design changes. In various embodiments, primary outputs of a new design are compared for logical equivalence to corresponding primary outputs of a prior implementation. If the logic is equivalent, the implementation of the primary outputs from the prior implementation is reused to implement the corresponding primary outputs of the new design.
摘要翻译：一种实现增量式设计变更的方法和装置。在各种实施例中，将新设计的主输出与先前实现的相应主输出进行逻辑等价比较。如果逻辑是等价的，则先前实现的主要输出的实现被重用以实现新设计的相应主要输出。

5. 发明授权

US06417689B1 Method and apparatus for placing output signals having different voltage levels on output pins of a programmable logic device 有权
标题翻译：用于将具有不同电压电平的输出信号放置在可编程逻辑器件的输出引脚上的方法和装置
公开(公告)号：US06417689B1
公开(公告)日：2002-07-09
申请号：US09766317
申请日：2001-01-16
申请人： Gitu Jain
发明人： Gitu Jain
IPC分类号： G06F738
CPC分类号： H03K19/17744 , G06F17/5072 , H03K19/17788
摘要： A method and apparatus for placing output signals having different voltage levels on output pins of a programmable logic device (PLD). The PLD includes a plurality of function blocks (FBs), and each FB includes one or more output pins. The output signals are organized into logical output banks (LOBs), the output signals in each LOB having a common voltage level. Each of the FBs is associated with an LOB. For each FB, one or more unplaced signals are selected for placement in the FB as a function of a number of unplaced output signals in the LOB with which the FB is associated (“current LOB”), a number of output pins in FBs associated with LOBs other than the current LOB, and a number of output pins in all FBs that are associated with the current LOB and that have no assigned output signals.
摘要翻译：一种用于将具有不同电压电平的输出信号放置在可编程逻辑器件（PLD）的输出引脚上的方法和装置。 PLD包括多个功能块（FB），并且每个FB包括一个或多个输出引脚。输出信号被组织成逻辑输出组（LOB），每个LOB中的输出信号具有公共电压电平。每个FB都与一个LOB相关联。对于每个FB，选择一个或多个未放置的信号来放置在FB中，作为与FB相关联的LOB中的未放置输出信号的数量（“当前LOB”）的函数，FB中的输出引脚数量相关联与当前LOB以外的LOB以及与当前LOB相关联并且没有分配的输出信号的所有FB中的多个输出引脚。

6. 发明授权

US6038386A Method for controlling power and slew in a programmable logic device 失效
标题翻译：用于在可编程逻辑器件中控制功率和转换的方法
公开(公告)号：US6038386A
公开(公告)日：2000-03-14
申请号：US918731
申请日：1997-08-21
申请人： Gitu Jain
发明人： Gitu Jain
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/78
摘要： A method for controlling power consumption and output slew rate in a programmable logic device, which is programmable to emulate a user-defined logic function. After placing and routing the user-defined logic function such that a plurality of paths are assigned to associated resources of the programmable logic device, a group of the resources associated with at least one path of the logic function which is constrained by a user-defined timing specification is identified. These resources are sorted according to their respective power consumption. A first sub-group of the resources is then identified which, when operated in a low power mode, minimizes power consumption of the programmable logic device while satisfying the user-defined timing specifications of all paths. Also, a second sub-group of the resources is identified which, when operated in a slow slew mode, minimizes noise at the output terminals of the programmable logic device while satisfying the user-defined timing specifications of all paths ending at that output terminal. A target PLD is then programmed in accordance with the placement arrangement, and the resources of the first and second groups are set to low power mode and slow slew mode, respectively.
摘要翻译：一种用于控制可编程逻辑器件中的功耗和输出转换速率的方法，其可编程以模拟用户定义的逻辑功能。在放置和路由用户定义的逻辑功能之后，使得多个路径被分配给可编程逻辑设备的相关资源，与由用户定义的约束的逻辑功能的至少一个路径相关联的资源组确定时序规范。这些资源根据各自的功耗进行排序。然后识别资源的第一子组，当以低功率模式操作时，可以最小化可编程逻辑器件的功耗，同时满足用户定义的所有路径的定时规范。此外，识别资源的第二子组，当以慢速转换模式操作时，可以将可编程逻辑器件的输出端子处的噪声最小化，同时满足在该输出端子处结束的所有路径的用户定义的定时规格。然后根据放置布置来编程目标PLD，并且分别将第一和第二组的资源设置为低功率模式和慢速转换模式。

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