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1. 发明授权

US07797665B1 Patterns for routing nets in a programmable logic device 有权
标题翻译：用于在可编程逻辑器件中路由网络的模式
公开(公告)号：US07797665B1
公开(公告)日：2010-09-14
申请号：US11999559
申请日：2007-12-06
申请人： Hui Xu , Vinay Verma , Anirban Rahut , Jason H. Anderson , Sandor S. Kalman
发明人： Hui Xu , Vinay Verma , Anirban Rahut , Jason H. Anderson , Sandor S. Kalman
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Nets of a logic design are efficiently routed in a programmable logic device, which includes multiple types of programmable interconnects. Patterns are read from a library in a storage device. Each pattern includes an ordered set of the types of the programmable interconnects. A path is determined from the source to the destination for each net of the logic design. The path is through a sequence of the programmable interconnects having types that correspond to each type in the ordered set of a selected pattern. A description is output of the path for each of the nets.
摘要翻译：逻辑设计的网络可编程逻辑器件有效路由，可编程逻辑器件包括多种类型的可编程互连。从存储设备中的库中读取模式。每个模式包括可编程互连类型的有序集合。对于逻辑设计的每个网络，从源到目的地确定路径。该路径通过可编程互连序列，其具有对应于所选模式的有序集合中的每种类型的类型。描述是每个网络的路径的输出。

2. 发明授权

US07134112B1 Incremental routing in integrated circuit design 有权
标题翻译：集成电路设计中的增量路由
公开(公告)号：US07134112B1
公开(公告)日：2006-11-07
申请号：US10624615
申请日：2003-07-21
申请人： Jason H. Anderson , Vinay Verma , Sandor S. Kalman
发明人： Jason H. Anderson , Vinay Verma , Sandor S. Kalman
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method for completing the routing of a partially routed design is provided. The unrouted pins are routed to generate a first plurality of nets that may contain shorts or overlaps between the nets. The nets are analyzed to obtain timing information, and then divided into a set of critical and a set of non-critical nets. The non-critical nets are hidden, and the critical nets are rerouted to remove overlaps. The non-critical nets are then unhidden. The non-critical nets and rerouted critical nets are then rerouted so as to remove overlaps.
摘要翻译：提供了完成部分路由设计路由的方法。未路由的引脚被路由以产生可以在网之间包含短路或重叠的第一多个网。对网络进行分析以获得定时信息，然后分为一组关键网络和一组非关键网络。非关键网络被隐藏，关键网络被重新路由以消除重叠。然后，非关键网络将被禁止。然后重新路由非关键网络和重新路由的关键网络，以消除重叠。

3. 发明授权

US07111268B1 Post-layout optimization in integrated circuit design 有权
标题翻译：集成电路设计后布局优化
公开(公告)号：US07111268B1
公开(公告)日：2006-09-19
申请号：US10644132
申请日：2003-08-20
申请人： Jason H. Anderson , Sandor S. Kalman , Vinay Verma
发明人： Jason H. Anderson , Sandor S. Kalman , Vinay Verma
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077
摘要： A method for post-layout timing optimization is disclosed. The method performs timing analysis on a design to obtain timing information such as critical paths and slack values. Incremental placement based on the timing information is performed. A new routed design is generated by applying incremental routing to the result of incremental placement. The routed design is stored if its performance is better than the previous routed design. The above steps are repeated until a predetermined criterion is met.
摘要翻译：公开了一种布局后定时优化的方法。该方法对设计执行定时分析以获得诸如关键路径和松弛值的定时信息。执行基于定时信息的增量放置。通过将增量路由应用于增量放置结果来生成新的路由设计。如果路由设计的性能优于先前的路由设计，则存储路由设计。重复上述步骤直到满足预定标准。

4. 发明授权

US08312409B1 Multi-threaded deterministic router 有权
标题翻译：多线程确定性路由器
公开(公告)号：US08312409B1
公开(公告)日：2012-11-13
申请号：US12718945
申请日：2010-03-05
申请人： Gitu Jain , Vinay Verma , Taneem Ahmed , Sandor S. Kalman , Sanjeev Kwatra , Christopher H. Kingsley , Jason H. Anderson , Satyaki Das
发明人： Gitu Jain , Vinay Verma , Taneem Ahmed , Sandor S. Kalman , Sanjeev Kwatra , Christopher H. Kingsley , Jason H. Anderson , Satyaki Das
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5054
摘要： A method is described that includes: determining that nets of the circuit design comprise overlap, where the overlap indicates that at least two of the nets of the circuit design use a same routing resource; dividing the nets with overlap among a plurality of buckets, where for each bucket, a net of the bucket does not overlap any other net in the bucket; sequentially processing each bucket by unrouting and rerouting, via at least one processor, nets in the bucket; and storing routing information specifying routes for nets of the circuit design.
摘要翻译：描述了一种方法，其包括：确定电路设计的网络包括重叠，其中重叠指示电路设计的网络中的至少两个使用相同的路由资源; 在多个桶之间用重叠划分网，其中对于每个桶，桶的网不与桶中的任何其他网重叠; 通过至少一个处理器，通过在桶中的网络进行路由和重新路由来顺序地处理每个桶; 并存储指定电路设计网络的路由的路由信息。

5. 发明授权

US09003413B1 Thread synchronization by transitioning threads to spin lock and sleep state 有权
标题翻译：线程同步通过转换线程来旋转锁定和睡眠状态
公开(公告)号：US09003413B1
公开(公告)日：2015-04-07
申请号：US12568558
申请日：2009-09-28
申请人： Jason H. Anderson , Taneem Ahmed , Sandor S. Kalman
发明人： Jason H. Anderson , Taneem Ahmed , Sandor S. Kalman
IPC分类号： G06F9/46 , H04L12/26
CPC分类号： H04L12/2634 , G06F9/52
摘要： A method, apparatus, and computer readable medium for synchronizing a main thread and a slave thread executing on a processor system are disclosed. For example, the method includes the following elements: transitioning the slave thread from a sleep state to a spin-lock state in response to a wake-up message from the main thread; transitioning the slave thread out of the spin-lock state to process a first work unit from the main thread; determining, at the main thread, an elapsed time period until receipt of a second work unit for the slave thread; transitioning the slave thread to the spin-lock state if the elapsed time period satisfies a threshold time period; and transitioning the slave thread to the sleep state if the elapsed time period does not satisfy the threshold time period.
摘要翻译：公开了一种用于同步处理器系统上执行的主线程和从线程的方法，装置和计算机可读介质。例如，该方法包括以下元件：响应于来自主线程的唤醒消息将从线程从睡眠状态转换到自旋锁定状态; 将从线程转换到自旋锁定状态以从主线程处理第一工作单元; 在所述主线程处确定直到接收到所述从线程的第二工作单元的经过时间段; 如果经过时间段满足阈值时间段，则将从线程转换到自旋锁定状态; 以及如果经过时间段不满足阈值时间段，则将从线程转换到休眠状态。

6. 发明授权

US06877040B1 Method and apparatus for testing routability 有权
标题翻译：用于测试可布线性的方法和装置
公开(公告)号：US06877040B1
公开(公告)日：2005-04-05
申请号：US09624716
申请日：2000-07-25
申请人： Gi-Joon Nam , Sandor S. Kalman , Jason H. Anderson , Rajeev Jayaraman , Sudip K. Nag , Jennifer Zhuang
发明人： Gi-Joon Nam , Sandor S. Kalman , Jason H. Anderson , Rajeev Jayaraman , Sudip K. Nag , Jennifer Zhuang
IPC分类号： G06F15/173
CPC分类号： G06F17/5077 , G06F17/5054
摘要： A method and apparatus for determining routing feasibility of a plurality of nets. Each net has an associated set of one or more routing solutions, wherein each solution specifies one or more routing resources consumed by the net. A liveness Boolean function is generated having variables that represent respective net/solution pairs. If there exists a set of values for the variables such that at least one of the variables for each net is logically true, then the liveness function is true. An exclusivity function is generated using the variables that represent the net/solution pairs. If there exists at least one set of values for the variables such that no resource is used is by more than a predetermined number of nets, then the exclusivity function is true. The nets are routable using the provided solutions if there is one set of values for the variables such that both the liveness and exclusivity functions are true.
摘要翻译：一种用于确定多个网络的路由可行性的方法和装置。每个网络具有一组或多个路由解决方案，其中每个解决方案指定网络所消耗的一个或多个路由资源。生成具有表示相应的净/解对对的变量的活力布尔函数。如果存在一组变量的值，使得每个网络的至少一个变量在逻辑上为真，那么活动函数为真。使用表示网络/解决方案对的变量生成排他性功能。如果存在变量的至少一组值，使得没有资源被使用超过预定数量的网络，则排他性功能是真实的。如果有一组变量的值，使用提供的解决方案，网络可以路由，以使活动和排他性功能都是真实的。

7. 发明授权

US06484298B1 Method and apparatus for automatic timing-driven implementation of a circuit design 有权
标题翻译：自动定时驱动实现电路设计的方法和装置
公开(公告)号：US06484298B1
公开(公告)日：2002-11-19
申请号：US09574641
申请日：2000-05-18
申请人： Sudip K. Nag , Kamal Chaudhary , Jason H. Anderson , Madabhushi V. R. Chari , Sandor S. Kalman
发明人： Sudip K. Nag , Kamal Chaudhary , Jason H. Anderson , Madabhushi V. R. Chari , Sandor S. Kalman
IPC分类号： G06F1750
CPC分类号： G06F17/5072 , G06F17/5077
摘要： A method and apparatus for automatic, timing-driven implementation of a circuit design. In one embodiment, the different phases of implementing a circuit design are iteratively performed using timing constraints that are automatically and dynamically generated in each iteration. The process aids in identifying and achieving a maximum performance level of the implemented design. In another embodiment, selected numbers of critical connections are used to dynamically vary the timing constraint. In general, a number of connections is automatically selected from the circuit design and used to derive a new timing constraint to be applied in the next iteration. Slack values associated with paths in the design are also used in deriving the new timing constraint.
摘要翻译：一种用于电路设计的自动定时驱动实现的方法和装置。在一个实施例中，使用在每次迭代中自动和动态生成的时序约束来迭代地执行实现电路设计的不同阶段。该过程有助于确定并实现实施设计的最高性能水平。在另一个实施例中，使用所选数量的关键连接来动态地改变时序约束。通常，从电路设计中自动选择多个连接，并用于导出将在下一次迭代中应用的新的时序约束。与设计中的路径相关联的松弛值也用于推导新的时序约束。

8. 发明授权

US07725868B1 Method and apparatus for facilitating signal routing within a programmable logic device 有权
标题翻译：用于促进可编程逻辑器件内的信号路由的方法和装置
公开(公告)号：US07725868B1
公开(公告)日：2010-05-25
申请号：US11983550
申请日：2007-11-09
申请人： Vinay Verma , Anirban Rahut , Sudip K. Nag , Jason H. Anderson , Rajeev Jayaraman
发明人： Vinay Verma , Anirban Rahut , Sudip K. Nag , Jason H. Anderson , Rajeev Jayaraman
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： H01L27/0207 , G06F17/5027 , G06F17/5077 , H01L27/11803
摘要： Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for each of the groups, the routing resources are of a same type. Pairs of the groups are related by an association of at least one routing resource in one group of a pair of groups capable of being electrically connected to at least one other routing resource in another group of the pair of groups.
摘要翻译：描述了在具有路由资源的可编程逻辑设备内促进信号路由的方法和装置。在一个示例中，路由资源被形成为其中对于每个组的路由资源是相同类型的组。这些组中的一组通过能够与一对组的另一组中的至少一个其他路由资源电连接的一组组中的至少一个路由资源的关联相关联。

9. 发明授权

US07306977B1 Method and apparatus for facilitating signal routing within a programmable logic device 有权
标题翻译：用于促进可编程逻辑器件内的信号路由的方法和装置
公开(公告)号：US07306977B1
公开(公告)日：2007-12-11
申请号：US10651808
申请日：2003-08-29
申请人： Vinay Verma , Anirban Rahut , Sudip K. Nag , Jason H. Anderson , Rajeev Jayaraman
发明人： Vinay Verma , Anirban Rahut , Sudip K. Nag , Jason H. Anderson , Rajeev Jayaraman
IPC分类号： H01L21/82
CPC分类号： H01L27/0207 , G06F17/5027 , G06F17/5077 , H01L27/11803
摘要： Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for each of the groups, the routing resources are of a same type. Pairs of the groups are related by an association of at least one routing resource in one group of a pair of groups capable of being electrically connected to at least one other routing resource in another group of the pair of groups.
摘要翻译：描述了在具有路由资源的可编程逻辑设备内促进信号路由的方法和装置。在一个示例中，路由资源被形成为其中对于每个组的路由资源是相同类型的组。这些组中的一组通过能够与一对组的另一组中的至少一个其他路由资源电连接的一组组中的至少一个路由资源的关联相关联。

10. 发明授权

US08205180B1 Method of and system for generating a logic configuration for an integrated circuit 有权
标题翻译：用于生成集成电路的逻辑配置的方法和系统
公开(公告)号：US08205180B1
公开(公告)日：2012-06-19
申请号：US12435886
申请日：2009-05-05
申请人： Jason H. Anderson , Qiang Wang
发明人： Jason H. Anderson , Qiang Wang
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5072 , G06F2217/84
摘要： A method of placing a circuit design in logic blocks of an integrated circuit is disclosed. The method comprises receiving a circuit design to be implemented in the logic blocks of the integrated circuit; determining clock skew for a clock tree providing clock signals to a plurality of memory elements of the integrated circuit; evaluating timing requirements associated with the circuit design; and transforming the circuit design to a placement configuration, wherein the placement configuration places the circuit design in the logic blocks of the integrated circuit according to the timing requirements of the circuit design and the clock skew for the clock tree.
摘要翻译：公开了一种将电路设计置于集成电路的逻辑块中的方法。该方法包括接收要在集成电路的逻辑块中实现的电路设计; 确定为所述集成电路的多个存储器元件提供时钟信号的时钟树的时钟偏移; 评估与电路设计相关的时序要求; 以及将所述电路设计转换成放置配置，其中所述放置配置根据所述电路设计的时序要求和所述时钟树的所述时钟偏移来将所述电路设计放置在所述集成电路的逻辑块中。

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