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1. 发明申请

US20080268624A1 Method of Fabricating Semiconductor Device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20080268624A1
公开(公告)日：2008-10-30
申请号：US11962386
申请日：2007-12-21
申请人： Noh Yeal Kwak , Min Sik Jang
发明人： Noh Yeal Kwak , Min Sik Jang
IPC分类号： H01L21/425
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/2658 , H01L21/823878 , H01L21/823892 , H01L27/0928
摘要： This invention relates to a method of fabricating a semiconductor device. A P well for a cell junction may be formed by performing an ion implantation process employing a zero tilt condition. Stress caused by collision between a dopant and a Si lattice within a semiconductor substrate may be minimized and, therefore stress remaining within the semiconductor substrate may be minimized. Accordingly, Number Of Program (NOP) fail by disturbance caused by stress remaining within a channel junction may be reduced. Further, a broad doping profile may be formed at the interface of trenches by using BF2 as the dopant when the P well is formed. A fluorine getter layer may be formed on an oxide film of the trench sidewalls and may be used as a boron diffusion barrier. Although a Spin On Dielectric (SOD) insulating layer may be used as an isolation layer, loss of boron (B) may be prevented. Accordingly, an additional ion implantation process for compensating for lost boron (B) may be omitted and a NOP disturbance characteristic may be improved.
摘要翻译：本发明涉及半导体器件的制造方法。可以通过执行使用零倾斜状态的离子注入工艺来形成用于电池结的P阱。由半导体衬底内的掺杂剂和Si晶格之间的碰撞引起的应力可能被最小化，因此可能使残留在半导体衬底内的应力最小化。因此，可能减少由通道结内的应力残留引起的干扰导致的程序编号（NOP）失败。此外，当形成P阱时，可以通过使用BF 2 N 2作为掺杂剂，在沟槽的界面处形成宽的掺杂分布。氟吸气剂层可以形成在沟槽侧壁的氧化物膜上，并且可以用作硼扩散阻挡层。虽然可以使用自旋介电（SOD）绝缘层作为隔离层，但是可以防止硼（B）的损失。因此，可以省略用于补偿失去的硼（B）的附加离子注入工艺，并且可以提高NOP干扰特性。

2. 发明申请

US20080124894A1 METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US20080124894A1
公开(公告)日：2008-05-29
申请号：US11614084
申请日：2006-12-21
申请人： Chul Young Ham , Noh Yeal Kwak
发明人： Chul Young Ham , Noh Yeal Kwak
IPC分类号： H01L21/762
CPC分类号： H01L21/31058 , H01L21/0217 , H01L21/02282 , H01L21/02337 , H01L21/3125 , H01L21/76237
摘要： A method of forming an isolation structure of a semiconductor device includes implanting dopants of a first type into a semiconductor substrate to form a doped region in the substrate. A mask layer is provided over the substrate and the doped region of the substrate. The mask layer is patterned to expose an isolation region of the substrate, the isolation region defining an active region, the isolation region and the active region being defined at least partly within the doped region. Dopants of a second type are implanted at an edge of the active region as defined by the isolation region. The isolation region of the semiconductor substrate is etched to form an isolation trench having a depth that extends below a depth of the doped region. Dopants of a third type are implanted on sidewalls of the trench in order to minimize the dopants of the second type provided on the sidewalls of the isolation trench from migrating away from the sidewalls. The trenches are filled with a dielectric layer to form an isolation structure.
摘要翻译：形成半导体器件的隔离结构的方法包括将第一类型的掺杂剂注入到半导体衬底中以在衬底中形成掺杂区域。在衬底和衬底的掺杂区域上提供掩模层。图案化掩模层以暴露衬底的隔离区域，隔离区域限定有源区域，隔离区域和有源区域至少部分地限定在掺杂区域内。第二类型的掺杂剂被注入在由隔离区限定的有源区的边缘处。蚀刻半导体衬底的隔离区域以形成具有在掺杂区域的深度之下延伸的深度的隔离沟槽。将第三类型的掺杂剂注入到沟槽的侧壁上，以使设置在隔离沟槽的侧壁上的第二类型的掺杂剂最小化，从而离开侧壁迁移。沟槽填充有介电层以形成隔离结构。

3. 发明授权

US07018885B2 Method of manufacturing semiconductor devices 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07018885B2
公开(公告)日：2006-03-28
申请号：US11076759
申请日：2005-03-10
申请人： Noh Yeal Kwak
发明人： Noh Yeal Kwak
IPC分类号： H01L21/8238 , H01L21/265
CPC分类号： H01L27/11521 , H01L21/02052 , H01L21/26506 , H01L21/26513 , H01L21/76224 , H01L21/823412 , H01L21/823481 , H01L29/105
摘要： Disclosed is a method of manufacturing semiconductor devices. Before the threshold voltage ion is implanted, an inert ion having no electrical properties is implanted into the bottom of a channel region to form an anti-diffusion layer. Therefore, it is possible to prevent diffusion of an ion for adjusting the threshold voltage into the bottom of the channel region, occurring in a subsequent annealing process, and prohibit behavior of the ion at the channel region when a high voltage is applied to a P well. Further, the anti-diffusion layer serves as a layer to gather defects, etc. existing in the semiconductor substrate. Also, as the amount of channel ion could be adjusted by controlling the implantation depth of the inert ion, it is possible to control the threshold voltage of the device depending on higher integration.
摘要翻译：公开了半导体器件的制造方法。在注入阈值电压离子之前，将不具有电性能的惰性离子注入沟道区域的底部以形成反扩散层。因此，可以防止用于将阈值电压调整到在随后的退火工序中发生的沟道区域的底部的离子的扩散，并且当向P施加高电压时禁止在沟道区域处的离子的行为好。此外，抗扩散层用作收集存在于半导体衬底中的缺陷等的层。另外，由于可以通过控制惰性离子的注入深度来调节通道离子的量，所以可以根据更高的积分来控制器件的阈值电压。

4. 发明授权

US06927150B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06927150B2
公开(公告)日：2005-08-09
申请号：US10618290
申请日：2003-07-11
申请人： Noh Yeal Kwak
发明人： Noh Yeal Kwak
IPC分类号： H01L21/76 , H01L21/223 , H01L21/265 , H01L21/28 , H01L21/306 , H01L21/336 , H01L21/761 , H01L21/8247 , H01L27/115 , H01L29/10 , H01L29/788 , H01L29/792 , H01L21/04
CPC分类号： H01L21/02052 , H01L21/223 , H01L21/26513 , H01L21/28273 , H01L29/105 , H01L29/66825
摘要： Disclosed is a method of manufacturing a semiconductor device. In ion implantation process for controlling the threshold voltage of the transistor or the semiconductor device such as a flash memory cell, the dose of the impurity capable of securing the uniformity is implanted by minimum. The retained dose of the impurity is controlled by out gassing the implanted impurity by means of a cleaning process. Therefore, a uniform distribution characteristic of the implanted impurity could be obtained. A transistor or a flash memory cell of a low operating voltage could be manufactured.
摘要翻译：公开了半导体器件的制造方法。在用于控制晶体管或诸如闪速存储器单元的半导体器件的阈值电压的离子注入工艺中，能够最小地植入能够确保均匀性的杂质的剂量。杂质的保留剂量是通过清洗过程来排出注入的杂质来控制的。因此，可以获得注入杂质的均匀分布特性。可以制造低工作电压的晶体管或闪存单元。

5. 发明授权

US07429519B2 Method of forming isolation layer of semiconductor device 有权
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US07429519B2
公开(公告)日：2008-09-30
申请号：US11614084
申请日：2006-12-21
申请人： Chul Young Ham , Noh Yeal Kwak
发明人： Chul Young Ham , Noh Yeal Kwak
IPC分类号： H01L21/76
CPC分类号： H01L21/31058 , H01L21/0217 , H01L21/02282 , H01L21/02337 , H01L21/3125 , H01L21/76237
摘要： A method of forming an isolation structure of a semiconductor device includes implanting dopants of a first type into a semiconductor substrate to form a doped region in the substrate. A mask layer is provided over the substrate and the doped region of the substrate. The mask layer is patterned to expose an isolation region of the substrate, the isolation region defining an active region, the isolation region and the active region being defined at least partly within the doped region. Dopants of a second type are implanted at an edge of the active region as defined by the isolation region. The isolation region of the semiconductor substrate is etched to form an isolation trench having a depth that extends below a depth of the doped region. Dopants of a third type are implanted on sidewalls of the trench in order to minimize the dopants of the second type provided on the sidewalls of the isolation trench from migrating away from the sidewalls. The trenches are filled with a dielectric layer to form an isolation structure.
摘要翻译：形成半导体器件的隔离结构的方法包括将第一类型的掺杂剂注入到半导体衬底中以在衬底中形成掺杂区域。在衬底和衬底的掺杂区域上提供掩模层。图案化掩模层以暴露衬底的隔离区域，隔离区域限定有源区域，隔离区域和有源区域至少部分地限定在掺杂区域内。第二类型的掺杂剂被注入在由隔离区限定的有源区的边缘处。蚀刻半导体衬底的隔离区域以形成具有在掺杂区域的深度之下延伸的深度的隔离沟槽。将第三类型的掺杂剂注入到沟槽的侧壁上，以使设置在隔离沟槽的侧壁上的第二类型的掺杂剂最小化，从而离开侧壁迁移。沟槽填充有介电层以形成隔离结构。

6. 发明授权

US06753232B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06753232B2
公开(公告)日：2004-06-22
申请号：US10139329
申请日：2002-05-07
申请人： Noh-Yeal Kwak , Sang Wook Park
发明人： Noh-Yeal Kwak , Sang Wook Park
IPC分类号： H01L21336
CPC分类号： H01L21/265 , H01L21/2236 , H01L21/2652 , H01L21/26586 , H01L29/4941
摘要： The present invention discloses a method for fabricating a semiconductor device. A stabilized junction is formed by simultaneously adjusting diffusion in a channel direction and a depth direction by restricting transient enhanced diffusion and oxidation enhanced diffusion, and reducing a short channel effect and diffusion in the depth direction, by positioning a nitrified oxide film between a gate electrode and a nitride film spacer formed at side walls of the gate electrode in order to remove defects generated due to stress differences between the gate electrode and the nitride film spacer in a formation process of a PMOS transistor. It is thus possible to form a device having an ultra shallow junction which is not influenced by miniaturization.
摘要翻译：本发明公开了一种半导体器件的制造方法。通过在栅电极之间定位硝化氧化膜，通过同时调节通道方向和深度方向上的扩散，通过限制瞬时增强的扩散和氧化增强的扩散以及减小短沟道效应和深度方向的扩散来形成稳定的结以及形成在栅电极的侧壁处的氮化物膜间隔物，以便在PMOS晶体管的形成过程中消除由于栅电极和氮化物膜间隔物之间的应力差而产生的缺陷。因此，可以形成不受小型化影响的具有超浅结的装置。

7. 发明授权

US06472273B2 Method of manufacturing a flash memory device 失效
标题翻译：制造闪存装置的方法
公开(公告)号：US06472273B2
公开(公告)日：2002-10-29
申请号：US09875734
申请日：2001-06-06
申请人： Byung Hee Cho , Noh Yeal Kwak
发明人： Byung Hee Cho , Noh Yeal Kwak
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/66825
摘要： A method of manufacturing a flash memory device includes the steps of sequentially forming a tunnel oxide film and a first polysilicon layer on a semiconductor substrate in which a device separation film is formed and then patterning the tunnel oxide film and the first polysilicon layer to form a floating gate; forming a mask so that a portion in which a source region will be formed can be exposed and then removing the device separation film at the exposed portion; forming a dielectric film including a lower oxide film, a nitride film, and an upper oxide film on the entire structure; performing an annealing process; then forming a second polysilicon layer on the dielectric film; sequentially removing the polysilicon layer, the upper oxide film, and the nitride film in a portion in which a source region and a drain region will be formed, and injecting impurity ions into the semiconductor substrate at a portion in which the lower oxide film remains to form a source region and a drain region; after removing the remaining lower oxide film, sequentially forming a third polysilicon layer and a tungsten silicide layer on the entire structure and then patterning the third polysilicon layer and the tungsten silicide layer to form a control gate; and performing an annealing process for activating the impurity ions injected into the source region and the drain region.
摘要翻译：制造闪速存储器件的方法包括以下步骤：在其上形成器件分离膜的半导体衬底上依次形成隧道氧化物膜和第一多晶硅层，然后对隧道氧化物膜和第一多晶硅层进行构图，浮门形成掩模，使得其中将形成源极区的部分可以暴露，然后在暴露部分移除器件分离膜; 在整个结构上形成包括低氧化物膜，氮化物膜和上氧化膜的电介质膜; 进行退火处理; 然后在介电膜上形成第二多晶硅层; 在其中将形成源极区和漏极区的部分中顺序地去除多晶硅层，上氧化物膜和氮化物膜，并且在低氧化膜保留的部分将杂质离子注入到半导体衬底中形成源极区域和漏极区域; 在除去剩余的低氧化物膜之后，在整个结构上依次形成第三多晶硅层和硅化钨层，然后构图第三多晶硅层和硅化钨层以形成控制栅极; 并且执行用于激活注入到源极区域和漏极区域中的杂质离子的退火处理。

8. 发明申请

US20080003788A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20080003788A1
公开(公告)日：2008-01-03
申请号：US11617188
申请日：2006-12-28
申请人： Chul Young Ham , Noh Yeal Kwak
发明人： Chul Young Ham , Noh Yeal Kwak
IPC分类号： H01L21/425
CPC分类号： H01L29/6659 , H01L27/115 , H01L27/11526 , H01L27/11534
摘要： A method of manufacturing a semiconductor device includes the steps of forming a gate for a high voltage transistor on a semiconductor substrate, forming a Double Doped Drain (DDD) junction in the semiconductor substrate by means of an ion implantation process employing a DDD mask, and removing point defects, which have occurred in the DDD junction during the ion implantation process, by means of a Defect Recovery Anneal (DRA) process.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成用于高压晶体管的栅极，通过使用DDD掩模的离子注入工艺在半导体衬底中形成双掺杂漏极（DDD）结;以及通过缺陷恢复退火（DRA）过程去除在离子注入过程中在DDD结中发生的点缺陷。

9. 发明授权

US06699744B2 Method of forming a MOS transistor of a semiconductor device 有权
标题翻译：形成半导体器件的MOS晶体管的方法
公开(公告)号：US06699744B2
公开(公告)日：2004-03-02
申请号：US10172842
申请日：2002-06-17
申请人： Noh-yeal Kwak , Sang-wook Park
发明人： Noh-yeal Kwak , Sang-wook Park
IPC分类号： H01L218238
CPC分类号： H01L21/28061 , H01L21/26506 , H01L21/2658 , H01L21/26586 , H01L21/28247 , H01L21/28568 , H01L21/823842
摘要： The disclosure relates to a method of forming a MOS transistor of a semiconductor device and, more particularly, to a method of forming a PMOS transistor of a semiconductor device that minimizes temporary reinforcement and diffusion of dopants for controlling a threshold voltage and dopants for forming a gate electrode due to the selective oxidization of side walls of a conductive layer even though a post heat process is performed at a low temperature by implanting inert ions into the entire semiconductor substrate having a gate pattern including a conductive layer and a metal layer. Thus, the conductive layer and the metal layer are made to have different surface binding capacities to improve the characteristics, reliability and yield of the semiconductor device and to enable high integration of the semiconductor device.
摘要翻译：本公开涉及一种形成半导体器件的MOS晶体管的方法，更具体地说，涉及一种形成半导体器件的PMOS晶体管的方法，该半导体器件的最小化用于控制阈值电压的掺杂剂的临时增强和扩散以及用于形成即使通过在具有包括导电层和金属层的栅极图案的整个半导体衬底中注入惰性离子而在低温下进行后热处理，由于导电层的侧壁的选择性氧化，导致栅极电极的选择性氧化。因此，导电层和金属层被制成具有不同的表面结合能力，以改善半导体器件的特性，可靠性和产量，并且能够实现半导体器件的高集成度。

10. 发明授权

US06444522B1 Method of manufacturing a flash memory device with an antidiffusion region between well regions 失效
标题翻译：制造在井区之间具有防扩散区域的闪存装置的方法
公开(公告)号：US06444522B1
公开(公告)日：2002-09-03
申请号：US09716416
申请日：2000-11-21
申请人： Byung Hee Cho , Noh Yeal Kwak
发明人： Byung Hee Cho , Noh Yeal Kwak
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： There is disclosed a method of manufacturing a flash memory device. In order to solve the problems that a break down voltage between wells is reduced and an insulating characteristic between the wells is lowered due to degraded barrier characteristic between the wells, in a flash memory device employing a triple well structure, the present invention forms an anti-diffusion region for preventing diffusion of dopants between a P-well region and a N-well region by nitrogen ion implantation, thus improving the electrical characteristic of the device.
摘要翻译：公开了一种制造闪速存储器件的方法。为了解决在采用三重阱结构的闪速存储器件中，井之间的分解电压降低并且阱之间的绝缘特性由于阱之间的屏障特性劣化而降低的问题，本发明形成了一种抗扩散区域，用于通过氮离子注入防止掺杂剂在P阱区域和N阱区域之间的扩散，从而提高器件的电特性。

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