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1. 发明授权

US08609507B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08609507B2
公开(公告)日：2013-12-17
申请号：US13149365
申请日：2011-05-31
申请人： Tae Kyung Kim , Min Sik Jang , Sung Deok Kim
发明人： Tae Kyung Kim , Min Sik Jang , Sung Deok Kim
IPC分类号： H01L21/764
CPC分类号： H01L27/11524 , H01L21/7682
摘要： A semiconductor device includes gates formed over a semiconductor substrate that are spaced apart from one another and each have a stack structure of a tunnel insulation layer, a floating gate, a dielectric layer, a first conductive layer, and a metal silicide layer, a first insulation layer formed along the sidewalls of the gates and a surface of the semiconductor substrate between the gates and configured to have a height lower than the top of the metal silicide layer; and a second insulation layer formed along surfaces of the first insulation layer and surfaces of the metal silicide layer and configured to cover an upper portion of a space between the gates, wherein an air gap is formed between the gates.
摘要翻译：半导体器件包括形成在半导体衬底上的彼此间隔开的栅极，并且每个栅极具有隧道绝缘层，浮置栅极，电介质层，第一导电层和金属硅化物层的堆叠结构，第一沿着所述栅极的侧壁形成的绝缘层和所述栅极之间的所述半导体衬底的表面，并且被配置为具有低于所述金属硅化物层的顶部的高度; 以及第二绝缘层，其沿着所述第一绝缘层的表面和所述金属硅化物层的表面形成并且被构造成覆盖所述栅极之间的空间的上部，其中在所述栅极之间形成气隙。

2. 发明申请

US20120280300A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120280300A1
公开(公告)日：2012-11-08
申请号：US13149365
申请日：2011-05-31
申请人： Tae Kyung KIM , Min Sik Jang , Sang Deok Kim
发明人： Tae Kyung KIM , Min Sik Jang , Sang Deok Kim
IPC分类号： H01L29/788 , H01L21/283
CPC分类号： H01L27/11524 , H01L21/7682
摘要： A semiconductor device includes gates formed over a semiconductor substrate that are spaced apart from one another and each have a stack structure of a tunnel insulation layer, a floating gate, a dielectric layer, a first conductive layer, and a metal silicide layer, a first insulation layer formed along the sidewalls of the gates and a surface of the semiconductor substrate between the gates and configured to have a height lower than the top of the metal silicide layer; and a second insulation layer formed along surfaces of the first insulation layer and surfaces of the metal silicide layer and configured to cover an upper portion of a space between the gates, wherein an air gap is formed between the gates.
摘要翻译：半导体器件包括形成在半导体衬底上的彼此间隔开的栅极，并且每个栅极具有隧道绝缘层，浮置栅极，电介质层，第一导电层和金属硅化物层的堆叠结构，第一沿着所述栅极的侧壁形成的绝缘层和所述栅极之间的所述半导体衬底的表面，并且被配置为具有低于所述金属硅化物层的顶部的高度; 以及第二绝缘层，其沿着所述第一绝缘层的表面和所述金属硅化物层的表面形成并且被构造成覆盖所述栅极之间的空间的上部，其中在所述栅极之间形成气隙。

3. 发明授权

US07858491B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07858491B2
公开(公告)日：2010-12-28
申请号：US11962386
申请日：2007-12-21
申请人： Noh Yeal Kwak , Min Sik Jang
发明人： Noh Yeal Kwak , Min Sik Jang
IPC分类号： H01L21/76
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/2658 , H01L21/823878 , H01L21/823892 , H01L27/0928
摘要： This invention relates to a method of fabricating a semiconductor device. A P well for a cell junction may be formed by performing an ion implantation process employing a zero tilt condition. Stress caused by collision between a dopant and a Si lattice within a semiconductor substrate may be minimized and, therefore stress remaining within the semiconductor substrate may be minimized. Accordingly, Number Of Program (NOP) fail by disturbance caused by stress remaining within a channel junction may be reduced. Further, a broad doping profile may be formed at the interface of trenches by using BF2 as the dopant when the P well is formed. A fluorine getter layer may be formed on an oxide film of the trench sidewalls and may be used as a boron diffusion barrier. Although a Spin On Dielectric (SOD) insulating layer may be used as an isolation layer, loss of boron (B) may be prevented. Accordingly, an additional ion implantation process for compensating for lost boron (B) may be omitted and a NOP disturbance characteristic may be improved.
摘要翻译：本发明涉及半导体器件的制造方法。可以通过执行使用零倾斜状态的离子注入工艺来形成用于电池结的P阱。由半导体衬底内的掺杂剂和Si晶格之间的碰撞引起的应力可能被最小化，因此可能使残留在半导体衬底内的应力最小化。因此，可能减少由通道结内的应力残留引起的干扰导致的程序编号（NOP）失败。此外，当形成P阱时，可以通过使用BF 2作为掺杂剂在沟槽的界面处形成宽的掺杂分布。氟吸气剂层可以形成在沟槽侧壁的氧化物膜上，并且可以用作硼扩散阻挡层。虽然可以使用自旋介电（SOD）绝缘层作为隔离层，但是可以防止硼（B）的损失。因此，可以省略用于补偿失去的硼（B）的附加离子注入工艺，并且可以提高NOP干扰特性。

4. 发明授权

US07632743B2 Method of manufacturing flash memory device 失效
标题翻译：制造闪存设备的方法
公开(公告)号：US07632743B2
公开(公告)日：2009-12-15
申请号：US11479332
申请日：2006-06-30
申请人： Min Sik Jang
发明人： Min Sik Jang
IPC分类号： H01L21/44
CPC分类号： H01L21/28273
摘要： A method of manufacturing a flash memory device includes forming a first polysilicon layer over a semiconductor substrate to form a floating gate. A tunnel dielectric layer is formed over the first polysilicon layer. A second polysilicon layer and a tungsten silicide layer are formed over the tunnel dielectric film to firm a control gate, the tungsten silicide layer having excess silicon. An upper portion of the tungsten silicide layer is oxidized to move the excess silicon away from an interface between the second polysilicon layer and the tungsten silicide.
摘要翻译：制造闪速存储器件的方法包括在半导体衬底上形成第一多晶硅层以形成浮栅。隧道介电层形成在第一多晶硅层上。在隧道电介质膜之上形成第二多晶硅层和硅化钨层，以固定控制栅极，硅化钨层具有多余的硅。硅化钨层的上部被氧化以使多余的硅离开第二多晶硅层和硅化钨之间的界面。

5. 发明申请

US20080206957A1 Method of Forming Isolation Layer of Semiconductor Memory Device 审中-公开
标题翻译：形成半导体存储器件隔离层的方法
公开(公告)号：US20080206957A1
公开(公告)日：2008-08-28
申请号：US11951308
申请日：2007-12-05
申请人： Kwang Hyun Yun , Min Sik Jang
发明人： Kwang Hyun Yun , Min Sik Jang
IPC分类号： H01L21/62
CPC分类号： H01L21/76232 , H01L27/115 , H01L27/11521
摘要： The present invention relates to a method of forming an isolation layer of a semiconductor memory device. After a trench is formed by etching a semiconductor substrate, a liner insulating film is formed from a DCS-HTO material having a similar wet etch rate to that of a PSZ film that gap fills an isolation layer, and the trench is gap filled with the PSZ film. Accordingly, in a subsequent etch process for EFH control of the isolation layer, residues do not remain on sidewalls of a conductive film for a floating gate, thereby improving electrical properties of devices.
摘要翻译：本发明涉及形成半导体存储器件的隔离层的方法。在通过蚀刻半导体衬底形成沟槽之后，由具有与蚀刻速率相似的湿蚀刻速率的DCS-HTO材料形成衬垫绝缘膜，该PSS膜间隙填充隔离层，并且沟槽填充有 PSZ电影。因此，在用于隔离层的EFH控制的后续蚀刻工艺中，残留物不会残留在用于浮置栅极的导电膜的侧壁上，从而改善器件的电性能。

6. 发明申请

US20070293026A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20070293026A1
公开(公告)日：2007-12-20
申请号：US11616023
申请日：2006-12-26
申请人： Min Sik Jang , Noh Yeal Kwak
发明人： Min Sik Jang , Noh Yeal Kwak
IPC分类号： H01L21/425
CPC分类号： H01L21/324 , H01L29/66575 , H01L29/78
摘要： A method of manufacturing a semiconductor device includes the step of performing an ion implantation process for implanting an impurity ion into a semiconductor substrate, and performing annealing in a state where temperature of respective portions of an annealing chamber are set differently in order to activate the impurity ion.
摘要翻译：一种制造半导体器件的方法包括以下步骤：将杂质离子注入到半导体衬底中进行离子注入工艺，并且在退火室的各部分的温度被不同地设定的状态下执行退火以激活杂质离子。

7. 发明授权

US07838421B2 Method of forming metal line of semiconductor device 失效
标题翻译：形成半导体器件金属线的方法
公开(公告)号：US07838421B2
公开(公告)日：2010-11-23
申请号：US12163374
申请日：2008-06-27
申请人： Min Sik Jang
发明人： Min Sik Jang
IPC分类号： H01L21/44
CPC分类号： H01L21/76897 , H01L21/76814 , H01L21/76831 , H01L27/11526 , H01L27/11529
摘要： A method of forming metal lines of a semiconductor device, comprising providing a semiconductor substrate in which a plurality of gates and junctions formed between the gates are included in a cell area and a peripheral area; forming an insulating layer over the semiconductor substrate including the gates; forming an etch protection layer over the insulating layer; etching the etch protection layer and the insulating layer, and gap-filling conductive material to form contact plugs contacting the junctions of the cell area; and, forming first metal lines contacting the contact plugs and forming second metal lines contacting the junctions of the peripheral area by etching the etch protection layer and the insulating layer.
摘要翻译：一种形成半导体器件的金属线的方法，包括提供半导体衬底，其中形成在所述栅极之间的多个栅极和结形成在所述半导体衬底中，所述半导体衬底包括在单元区域和外围区域中; 在包括所述栅极的所述半导体衬底上形成绝缘层; 在所述绝缘层上形成蚀刻保护层; 蚀刻蚀刻保护层和绝缘层，以及间隙填充导电材料以形成接触细胞区域的接合点的接触塞; 以及形成接触所述接触塞的第一金属线，并通过蚀刻所述蚀刻保护层和所述绝缘层，形成与所述周边区的接合部接触的第二金属线。

8. 发明申请

US20090181516A1 Method of Forming Isolation Layer of Semiconductor Device 审中-公开
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US20090181516A1
公开(公告)日：2009-07-16
申请号：US12131239
申请日：2008-06-02
申请人： Min Sik Jang
发明人： Min Sik Jang
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： A method of forming an isolation layer of a semiconductor device is disclosed. In the method according to one aspect, a semiconductor substrate having a trench formed therein is provided. A first insulating layer is formed over an entire surface of the semiconductor substrate including a surface of the trench. A passivation layer, preferably silicon, including oxygen is formed on a surface of the first insulating layer. A second insulating layer is formed on the passivation layer formed within the trench.
摘要翻译：公开了一种形成半导体器件隔离层的方法。在根据一个方面的方法中，提供了其中形成有沟槽的半导体衬底。在包括沟槽的表面的半导体衬底的整个表面上形成第一绝缘层。在第一绝缘层的表面上形成钝化层，优选包括氧的硅。在形成在沟槽内的钝化层上形成第二绝缘层。

9. 发明申请

US20070278561A1 FLASH MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：闪存存储器件及其制造方法
公开(公告)号：US20070278561A1
公开(公告)日：2007-12-06
申请号：US11751013
申请日：2007-05-19
申请人： Kwon HONG , Eun Shil Park , Min Sik Jang
发明人： Kwon HONG , Eun Shil Park , Min Sik Jang
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L29/513 , H01L29/7881
摘要： A non-volatile memory device has a gate dielectric film formed between a floating gate and a control gate. The gate dielectric film is formed by forming an oxide film and a ZrO2/Al2O3/ZrO2 (ZAZ) film. Accordingly, the reliability of non-volatile memory devices can be improved while securing a high coupling ratio.
摘要翻译：非易失性存储器件具有形成在浮置栅极和控制栅极之间的栅极电介质膜。栅电介质膜通过形成氧化物膜和ZrO 2 / Al 2 O 3 / ZrO 2 2 / （ZAZ）电影。因此，可以在确保高耦合比的同时提高非易失性存储器件的可靠性。

10. 发明授权

US07238574B1 Flash memory device and method of manufacturing the same 有权
标题翻译：闪存装置及其制造方法
公开(公告)号：US07238574B1
公开(公告)日：2007-07-03
申请号：US11479051
申请日：2006-06-30
申请人： Kwon Hong , Eun Shil Park , Min Sik Jang
发明人： Kwon Hong , Eun Shil Park , Min Sik Jang
IPC分类号： H01L21/8247
CPC分类号： H01L21/28273 , H01L29/513 , H01L29/7881
摘要： A non-volatile memory device has a gate dielectric film formed between a floating gate and a control gate. The gate dielectric film is formed by forming an oxide film and a ZrO2/Al2O3/ZrO2 (ZAZ) film. Accordingly, the reliability of non-volatile memory devices can be improved while securing a high coupling ratio.
摘要翻译：非易失性存储器件具有形成在浮置栅极和控制栅极之间的栅极电介质膜。栅电介质膜通过形成氧化物膜和ZrO 2 / Al 2 O 3 / ZrO 2 2 / （ZAZ）电影。因此，可以在确保高耦合比的同时提高非易失性存储器件的可靠性。

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