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1. 发明授权

US06699744B2 Method of forming a MOS transistor of a semiconductor device 有权
标题翻译：形成半导体器件的MOS晶体管的方法
公开(公告)号：US06699744B2
公开(公告)日：2004-03-02
申请号：US10172842
申请日：2002-06-17
申请人： Noh-yeal Kwak , Sang-wook Park
发明人： Noh-yeal Kwak , Sang-wook Park
IPC分类号： H01L218238
CPC分类号： H01L21/28061 , H01L21/26506 , H01L21/2658 , H01L21/26586 , H01L21/28247 , H01L21/28568 , H01L21/823842
摘要： The disclosure relates to a method of forming a MOS transistor of a semiconductor device and, more particularly, to a method of forming a PMOS transistor of a semiconductor device that minimizes temporary reinforcement and diffusion of dopants for controlling a threshold voltage and dopants for forming a gate electrode due to the selective oxidization of side walls of a conductive layer even though a post heat process is performed at a low temperature by implanting inert ions into the entire semiconductor substrate having a gate pattern including a conductive layer and a metal layer. Thus, the conductive layer and the metal layer are made to have different surface binding capacities to improve the characteristics, reliability and yield of the semiconductor device and to enable high integration of the semiconductor device.
摘要翻译：本公开涉及一种形成半导体器件的MOS晶体管的方法，更具体地说，涉及一种形成半导体器件的PMOS晶体管的方法，该半导体器件的最小化用于控制阈值电压的掺杂剂的临时增强和扩散以及用于形成即使通过在具有包括导电层和金属层的栅极图案的整个半导体衬底中注入惰性离子而在低温下进行后热处理，由于导电层的侧壁的选择性氧化，导致栅极电极的选择性氧化。因此，导电层和金属层被制成具有不同的表面结合能力，以改善半导体器件的特性，可靠性和产量，并且能够实现半导体器件的高集成度。

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