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1. 发明授权

US09202532B2 Burst sequence control and multi-valued fuse scheme in memory device 有权
标题翻译：存储器件中的脉冲序列控制和多值保险丝方案
公开(公告)号：US09202532B2
公开(公告)日：2015-12-01
申请号：US13615063
申请日：2012-09-13
申请人： Myung Chan Choi
发明人： Myung Chan Choi
IPC分类号： G11C7/10 , G11C8/12 , G11C16/08
CPC分类号： G11C7/1018 , G11C7/1045 , G11C8/12 , G11C16/08
摘要： A decoder circuit, responsive to a burst sequence control signal, for accessing a memory location in a memory array. The decoder circuit receives an address signal and outputs a plurality of first select lines. Logic circuitry receives these first select lines and a burst sequence control signal and outputs a plurality of second select lines. When the bust sequence control signal is unasserted, the logic circuitry passes through to the plurality of second select lines the signals received on the plurality of first select lines. When the burst sequence control signal is asserted, the logic circuitry performs a logical operation on the signals received on the plurality of first select lines and outputs the result on the plurality of second select lines.
摘要翻译：响应于突发序列控制信号的解码器电路，用于访问存储器阵列中的存储器位置。解码器电路接收地址信号并输出多条第一选择线。逻辑电路接收这些第一选择线和突发序列控制信号并输出多条第二选择线。当胸部序列控制信号被无效时，逻辑电路将多个第一选择线上接收的信号传递到多个第二选择线。当突发序列控制信号被断言时，逻辑电路对在多个第一选择线上接收的信号执行逻辑运算，并将结果输出到多条第二选择线上。

2. 发明申请

US20090154278A1 MEMORY DEVICE WITH SELF-REFRESH OPERATIONS 失效
标题翻译：具有自我修复操作的存储设备
公开(公告)号：US20090154278A1
公开(公告)日：2009-06-18
申请号：US12332740
申请日：2008-12-11
申请人： Myung Chan-Choi , Seung-Moon Yoo , Arthur Kwon
发明人： Myung Chan-Choi , Seung-Moon Yoo , Arthur Kwon
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/406 , G11C8/10 , G11C8/18 , G11C11/40615 , G11C2211/4065
摘要： An apparatus and method for reducing power consumption within dynamic memory devices having internal self-refresh circuitry. The circuits for generating isolator control (ISO), pre-decoded row address (PXID) and/or word enable (WE) signals are configured in response to receipt of self-refresh and refresh counter signals to output different timing and sequencing when in self-refresh mode than when in normal mode of the memory device. Conventionally, ISO signals are controlled from a block selection circuit which also controls bit line equalization (BLEQ) and sense amplifier enable (SAPN). While in conventional circuits the PXID and WE signals are generated in response to the output of the address decoder and thus have a fixed timing in relation to the output of the address decoder. The use of different timing and sequencing can lower power consumption, such as by outputting fewer signal transitions per block during self-refresh.
摘要翻译：一种用于在具有内部自刷新电路的动态存储器件中降低功耗的装置和方法。用于产生隔离器控制（ISO），预解码行地址（PXID）和/或字使能（WE）信号的电路被配置为响应于接收到自刷新和刷新计数器信号，以在自身中输出不同的定时和排序 -refresh模式比在正常模式下的存储设备。传统上，ISO信号由也可以控制位线均衡（BLEQ）和读出放大器使能（SAPN）的块选择电路控制。而在常规电路中，PXID和WE信号是响应于地址译码器的输出产生的，因此与地址解码器的输出有固定的时序。使用不同的定时和排序可以降低功耗，例如在自刷新期间通过在每个块输出更少的信号转换。

3. 发明授权

US5748639A Multi-bit test circuits for integrated circuit memory devices and related methods 失效
标题翻译：用于集成电路存储器件的多位测试电路及相关方法
公开(公告)号：US5748639A
公开(公告)日：1998-05-05
申请号：US637358
申请日：1996-04-24
申请人： Myung-chan Choi , Churoo Park
发明人： Myung-chan Choi , Churoo Park
IPC分类号： G01R31/28 , G01R31/3185 , G11C29/00 , G11C29/14 , G11C29/34 , G11C29/38
CPC分类号： G11C29/38
摘要： A method for testing a plurality of data bits includes the steps of accepting the plurality of data bits at the test circuit, and comparing first and second data bits from the plurality of data bits to determine if the first and second data bits have a common data value. A first comparison signal is generated responsive to the comparison of the first and second data bits. The first comparison signal has a first logic state when the first and second data bits have a common data value and a second logic state when the first and second data bits have different data values. Third and fourth data bits from the plurality of data bits are compared to determine if the third and fourth data bits have a common data value. A second comparison signal is generated responsive to the comparison of the third and fourth data bits wherein the second comparison signal has the first logic state when the third and fourth data bits have a common data value and the second logic state when the third and fourth data bits have different data values.
摘要翻译：一种用于测试多个数据位的方法包括以下步骤：在测试电路处接受多个数据位，并且从多个数据位中比较第一和第二数据位，以确定第一和第二数据位是否具有公共数据值。响应于第一和第二数据位的比较产生第一比较信号。当第一和第二数据位具有公共数据值时，第一比较信号具有第一逻辑状态，当第一和第二数据位具有不同的数据值时，第一比较信号具有第一逻辑状态。比较来自多个数据位的第三和第四数据位，以确定第三和第四数据位是否具有公共数据值。响应于第三和第四数据比特的比较产生第二比较信号，其中当第三和第四数据比特具有公共数据值时，第二比较信号具有第一逻辑状态，当第三和第四数据位具有不同的数据值。

4. 发明申请

US20140071770A1 Burst Sequence Control And Multi-Valued Fuse Scheme In Memory Device 有权
标题翻译：存储器件中的突发序列控制和多值保险丝方案
公开(公告)号：US20140071770A1
公开(公告)日：2014-03-13
申请号：US13615063
申请日：2012-09-13
申请人： Myung Chan Choi
发明人： Myung Chan Choi
IPC分类号： G11C7/10 , G11C8/10
CPC分类号： G11C7/1018 , G11C7/1045 , G11C8/12 , G11C16/08
摘要： A decoder circuit, responsive to a burst sequence control signal, for accessing a memory location in a memory array. The decoder circuit receives an address signal and outputs a plurality of first select lines. Logic circuitry receives these first select lines and a burst sequence control signal and outputs a plurality of second select lines. When the bust sequence control signal is unasserted, the logic circuitry passes through to the plurality of second select lines the signals received on the plurality of first select lines. When the burst sequence control signal is asserted, the logic circuitry performs a logical operation on the signals received on the plurality of first select lines and outputs the result on the plurality of second select lines.
摘要翻译：响应于突发序列控制信号的解码器电路，用于访问存储器阵列中的存储器位置。解码器电路接收地址信号并输出多条第一选择线。逻辑电路接收这些第一选择线和突发序列控制信号并输出多条第二选择线。当胸部序列控制信号被无效时，逻辑电路将多个第一选择线上接收的信号传递到多个第二选择线。当突发序列控制信号被断言时，逻辑电路对在多个第一选择线上接收的信号执行逻辑运算，并将结果输出到多条第二选择线上。

5. 发明授权

US07522464B2 Dynamic memory refresh configurations and leakage control methods 失效
标题翻译：动态内存刷新配置和泄漏控制方法
公开(公告)号：US07522464B2
公开(公告)日：2009-04-21
申请号：US11779716
申请日：2007-07-18
申请人： Seung-Moon Yoo , Myung Chan Choi , Sangho Shin , Sang-Kyun Han
发明人： Seung-Moon Yoo , Myung Chan Choi , Sangho Shin , Sang-Kyun Han
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/4094 , G11C29/783 , G11C29/83 , G11C29/832 , G11C2211/4061 , G11C2211/4065 , G11C2211/4067 , G11C2211/4068
摘要： Dynamic Random Access Memory (DRAM) circuits and methods are described for reducing leakage and increasing repaired yield. These objects are accomplished according to the invention by grouping refresh cycles within a single activation of power control, the use of limiting circuits or fuses to mitigate power losses associated with micro-bridging of bit-lines and word-lines, modulating the bit-line voltage at the end of precharge cycles, configuring refresh control circuits to use redundant word-lines in generating additional refresh cycles for redundant rows of memory cells, and combinations thereof. In one aspect, word-line fuses indicate modes of use as: unused, replacement, additional refresh, and replacement with additional refresh. The refresh control circuit utilizes these modes in combination with the X-address stored in the word-line fuses for controlling the generation of additional refresh cycles toward overcoming insufficient data retention intervals in select memory cell rows.
摘要翻译：描述了用于减少泄漏和提高修复产量的动态随机存取存储器（DRAM）电路和方法。根据本发明，通过在功率控制的单个激活中分组刷新周期，使用限制电路或熔丝来减轻与位线和字线的微桥接相关联的功率损耗，调制位线在预充电周期结束时配置刷新控制电路以使用冗余字线来产生冗余的存储器单元行的附加刷新周期，以及它们的组合。在一个方面，字线保险丝将使用模式指示为：未使用，替换，附加刷新以及附加刷新的替换。刷新控制电路利用这些模式与存储在字线保险丝中的X地址相组合，用于控制产生额外的刷新周期以克服选择存储单元行中的不充足的数据保留间隔。

6. 发明授权

US07324390B2 Low voltage operation dram control circuits 失效
标题翻译：低压运行控制电路
公开(公告)号：US07324390B2
公开(公告)日：2008-01-29
申请号：US11449170
申请日：2006-06-07
申请人： Myung Chan Choi
发明人： Myung Chan Choi
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C7/02 , G11C7/065 , G11C7/08 , G11C7/12 , G11C8/08 , G11C11/4074 , G11C11/4085 , G11C11/4094 , G11C2207/005 , G11C2207/2227
摘要： Circuits and methods are described for reducing leakage current and speeding access within dynamic random access memory circuit devices. A number of beneficial aspects are described. A circuit is described for an enhanced sense amplifier utilizing complementary drain transistors coupled to the sense or restore signals and driven by gate voltages which extend outside of the voltage range between VSS and VDD. The drain transistors are self reverse-biased in a standby mode. A method is also described for reducing leaking in non-complementary sense amplifiers by modifying the sense and restore gate voltages. Another aspect is a new negative word line method utilizing stacked pull-down transistors and a multi-step control circuit. In addition a level shifter scheme is described for preventing unwanted current flow between voltage sources while discharging control signal PX.
摘要翻译：描述了用于减少动态随机存取存储器电路器件中的泄漏电流和加速访问的电路和方法。描述了许多有益的方面。描述了一种利用互补漏极晶体管的增强型读出放大器的电路，所述互补漏极晶体管耦合到感测或恢复信号，并且通过延伸到V SS和V DD之间的电压范围之外的栅极电压驱动。 SUB>。漏极晶体管在待机模式下是自反向偏置的。还描述了一种通过修改感测和恢复栅极电压来减少非互补读出放大器中泄漏的方法。另一方面是利用堆叠式下拉晶体管和多级控制电路的新型负字线方法。此外，描述了电平移位器方案，用于在放电控制信号PX的同时防止电压源之间的不期望的电流流动。

7. 发明申请

US20070081405A1 LOW POWER MEMORY CONTROL CIRCUITS AND METHODS 失效
标题翻译：低功率存储器控制电路和方法
公开(公告)号：US20070081405A1
公开(公告)日：2007-04-12
申请号：US11534609
申请日：2006-09-22
申请人： Seung-Moon Yoo , Myung Chan Choi , Young Tae Kim , Sung Ju Son , Sang-Kyun Han , Sun Hyoung Lee
发明人： Seung-Moon Yoo , Myung Chan Choi , Young Tae Kim , Sung Ju Son , Sang-Kyun Han , Sun Hyoung Lee
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C7/065 , G11C7/08 , G11C7/20 , G11C8/08 , G11C8/10 , G11C8/12 , G11C8/14 , G11C11/406 , G11C11/4072 , G11C11/4074 , G11C11/4085 , G11C11/4087 , G11C2207/065 , G11C2207/2227 , G11C2211/4068 , H01L27/0207 , H01L27/10897
摘要： Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the invention describes lowering refresh current. An aspect describes reducing the standby current. An aspect of the invention describes lowering leakage resulting from duplicated circuits, such as row decoders and word line drivers. An aspect describes methods of performing early wake-up of source transistors. A number of source transistor control mechanisms are taught. Circuit layouts methods are taught for optimizing integrated circuit layouts using the source transistors.
摘要翻译：描述用于抑制集成电路漏电流的电路和方法。这些电路和方法中的许多特别适用于动态存储器电路。示例描述了用于产生虚拟电压的电源，接地或两者以及电源和接地源晶体管的使用。本发明的一个方面描述降低刷新电流。一方面描述了减少待机电流。本发明的一个方面描述了降低由诸如行解码器和字线驱动器的复制电路产生的泄漏。一方面描述了执行源晶体管的早期唤醒的方法。教授了许多源晶体管控制机制。教导了使用源极晶体管优化集成电路布局的电路布局方法。

8. 发明授权

US07705625B2 Source transistor configurations and control methods 失效
标题翻译：源晶体管配置和控制方法
公开(公告)号：US07705625B2
公开(公告)日：2010-04-27
申请号：US11483263
申请日：2006-07-06
申请人： Seung-Moon Yoo , Jae Hoon Yoo , Jeongduk Sohn , Sung Ju Son , Myung Chan Choi , Young Tae Kim , Oh Sang Yoon , Sang-Kyun Han
发明人： Seung-Moon Yoo , Jae Hoon Yoo , Jeongduk Sohn , Sung Ju Son , Myung Chan Choi , Young Tae Kim , Oh Sang Yoon , Sang-Kyun Han
IPC分类号： H03K19/094
CPC分类号： H03K19/0016 , G11C7/1045 , G11C11/4074 , G11C11/4076 , G11C2207/2227
摘要： Source transistor configurations are described for reducing leakage and delay within integrated circuits. Virtual power and ground nodes are supported with the use of stacked transistor configurations, such as a two transistor stack between a first virtual supply connection and VSS, and a second virtual supply connection and VDD. Gate drives of these stacked transistors are modulated with different voltage levels in response to the operating power mode of the circuit, for example active mode, active-standby mode, and deep power-down mode. Means for driving these source stacks are described. In one embodiment separate virtual nodes are adapted for different types of circuits, such as buffers, row address strobe, and column address strobe. Other techniques, such as directional placement of the transistors is also described.
摘要翻译：源晶体管配置被描述为减少集成电路内的泄漏和延迟。使用堆叠晶体管配置（例如在第一虚拟电源连接和VSS之间的两个晶体管堆叠）和第二虚拟电源连接和VDD之间来支持虚拟电源和接地节点。这些堆叠晶体管的栅极驱动器响应于电路的工作功率模式，例如主动模式，主动待机模式和深度掉电模式，以不同的电压电平进行调制。描述了用于驱动这些源堆栈的装置。在一个实施例中，单独的虚拟节点适用于不同类型的电路，例如缓冲器，行地址选通和列地址选通。还描述了诸如晶体管的定向放置的其它技术。

9. 发明授权

US07301322B2 CMOS constant voltage generator 失效
标题翻译： CMOS恒压发生器
公开(公告)号：US07301322B2
公开(公告)日：2007-11-27
申请号：US11033454
申请日：2005-01-10
申请人： Myung Chan Choi
发明人： Myung Chan Choi
IPC分类号： G05F3/26 , G05F3/16
CPC分类号： G05F3/247
摘要： A CMOS constant voltage generator circuit having input and output stages and at least one compensation stage. Each stage can comprise a single transistor or more typically a transistor stack. Current mirroring is performed between the input stage and compensation stage, as well as preferably between the input stage and output stage. The compensation stage also provides additional biasing to a transistor in the output stage to increase voltage regulation. Optionally, degeneration resistors (passive or active) are coupled to the source side, drain side, or a combination of source and drain sides in the compensation and output stages. Optionally, additional diode-coupled transistors are incorporated in the transistor stack of the output stage. The circuit provides accurate voltage reference (Vref) output with lowered sensitivity to temperature and supply voltage.
摘要翻译：一种具有输入和输出级以及至少一个补偿级的CMOS恒压发生器电路。每个级可以包括单个晶体管或更典型的晶体管堆叠。在输入级和补偿级之间以及优选在输入级和输出级之间执行电流镜像。补偿级还为输出级中的晶体管提供额外的偏置以增加电压调节。可选地，退化电阻器（无源或有源）耦合到补偿和输出级的源极侧，漏极侧或源极和漏极侧的组合。可选地，在输出级的晶体管堆叠中并入另外的二极管耦合晶体管。该电路为温度和电源电压的灵敏度降低提供精确的参考电压（V SUB REF）。

10. 发明授权

US5923612A Synchronous semiconductor memory device having macro command storage and execution method therefor 失效
标题翻译：具有宏命令存储及其执行方法的同步半导体存储器件
公开(公告)号：US5923612A
公开(公告)日：1999-07-13
申请号：US928595
申请日：1997-09-12
申请人： Chul Woo Park , Myung-Chan Choi
发明人： Chul Woo Park , Myung-Chan Choi
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F12/02 , G11C11/401 , G11C11/407 , G11C8/00
CPC分类号： G06F9/3836 , G06F9/3017 , G06F9/3802 , G06F9/3869
摘要： A semiconductor memory device having a macro command function includes a macro storage section for storing a series of external instructions synchronized with a clock signal and a plurality of interval data corresponding to a number of clock pulses occurring between the external instructions. A counter is also included for counting the clock pulses and for producing an output representing a number of clock pulses occurring since an initialization of the counter, and a selecting section is included for selecting between a current external instruction synchronized with the clock signal and the external instructions read out from the macro storage section. A comparing section is included for comparing the interval data of the appropriate external instruction from the macro storage section with an output of the counter, and a macro control section is included for controlling the macro storage section in response to a macro store command so that the series of external instructions and the number of clock pulses counted by the counter are stored in the macro storage section. The macro control means also controlling the selecting section to select the macro storage section in response to a macro execute command so that the series of instructions stored in the macro storage section are sequentially read out. The macro control also produces a next command when the interval data of the read-out external instruction equals the output of the counter.
摘要翻译：具有宏指令功能的半导体存储器件包括宏存储部分，用于存储与时钟信号同步的一系列外部指令以及对应于外部指令之间出现的时钟脉冲数的多个间隔数据。还包括计数器，用于对时钟脉冲进行计数，并产生表示自计数器初始化以来出现的时钟脉冲数的输出，并且包括选择部分，用于在与时钟信号同步的当前外部指令和外部指令从宏存储部分读出。包括比较部分，用于将来自宏存储部分的适当的外部指令的间隔数据与计数器的输出进行比较，并且包括宏控制部分，用于响应于宏存储命令来控制宏存储部分，一系列外部指令和计数器计数的时钟脉冲数存储在宏存储部分中。宏控制装置还响应宏执行命令控制选择部分选择宏存储部分，以便顺序地读出存储在宏存储部分中的一系列指令。当读出的外部指令的间隔数据等于计数器的输出时，宏控制也产生下一个命令。

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