专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06343036B1 Multi-bank dynamic random access memory devices having all bank precharge capability 有权
标题翻译：具有全部预充电能力的多组动态随机存取存储器件
公开(公告)号：US06343036B1
公开(公告)日：2002-01-29
申请号：US09157271
申请日：1998-09-18
申请人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
发明人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
IPC分类号： G11C700
CPC分类号： G11C7/1018 , G11C7/1045 , G11C7/1072 , G11C7/222 , G11C7/225 , G11C11/406 , G11C11/40618 , G11C11/4076 , G11C11/408 , G11C11/4082 , G11C11/4087 , G11C2207/2281
摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.
摘要翻译：能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到当锁存的逻辑电平是第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的去激活信号，使得响应于激活信号的所选存储器组在活动周期中工作，而未被选择的存储器组响应于灭活信号在预充电循环中工作。

2. 发明授权

US5748639A Multi-bit test circuits for integrated circuit memory devices and related methods 失效
标题翻译：用于集成电路存储器件的多位测试电路及相关方法
公开(公告)号：US5748639A
公开(公告)日：1998-05-05
申请号：US637358
申请日：1996-04-24
申请人： Myung-chan Choi , Churoo Park
发明人： Myung-chan Choi , Churoo Park
IPC分类号： G01R31/28 , G01R31/3185 , G11C29/00 , G11C29/14 , G11C29/34 , G11C29/38
CPC分类号： G11C29/38
摘要： A method for testing a plurality of data bits includes the steps of accepting the plurality of data bits at the test circuit, and comparing first and second data bits from the plurality of data bits to determine if the first and second data bits have a common data value. A first comparison signal is generated responsive to the comparison of the first and second data bits. The first comparison signal has a first logic state when the first and second data bits have a common data value and a second logic state when the first and second data bits have different data values. Third and fourth data bits from the plurality of data bits are compared to determine if the third and fourth data bits have a common data value. A second comparison signal is generated responsive to the comparison of the third and fourth data bits wherein the second comparison signal has the first logic state when the third and fourth data bits have a common data value and the second logic state when the third and fourth data bits have different data values.
摘要翻译：一种用于测试多个数据位的方法包括以下步骤：在测试电路处接受多个数据位，并且从多个数据位中比较第一和第二数据位，以确定第一和第二数据位是否具有公共数据值。响应于第一和第二数据位的比较产生第一比较信号。当第一和第二数据位具有公共数据值时，第一比较信号具有第一逻辑状态，当第一和第二数据位具有不同的数据值时，第一比较信号具有第一逻辑状态。比较来自多个数据位的第三和第四数据位，以确定第三和第四数据位是否具有公共数据值。响应于第三和第四数据比特的比较产生第二比较信号，其中当第三和第四数据比特具有公共数据值时，第二比较信号具有第一逻辑状态，当第三和第四数据位具有不同的数据值。

3. 发明授权

US5590086A Semiconductor memory having a plurality of I/O buses 失效
标题翻译：具有多个I / O总线的半导体存储器
公开(公告)号：US5590086A
公开(公告)日：1996-12-31
申请号：US580481
申请日：1995-12-29
申请人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
发明人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/4076 , G11C11/408 , G11C11/409 , G11C8/00
CPC分类号： G11C7/1018 , G11C11/406 , G11C11/40618 , G11C11/4076 , G11C11/408 , G11C11/4082 , G11C11/4087 , G11C7/1045 , G11C7/1072 , G11C7/222 , G11C7/225 , G11C2207/2281
摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.
摘要翻译：能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于灭活信号在预充电循环中工作。

4. 发明授权

US5838990A Circuit in a semiconductor memory for programming operation modes of the memory 失效
标题翻译：用于存储器的编程操作模式的半导体存储器中的电路
公开(公告)号：US5838990A
公开(公告)日：1998-11-17
申请号：US905562
申请日：1997-08-04
申请人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
发明人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/4076 , G11C11/408 , G11C11/409 , G06F9/00 , G06F13/16
CPC分类号： G11C7/1018 , G11C11/406 , G11C11/40618 , G11C11/4076 , G11C11/408 , G11C11/4082 , G11C11/4087 , G11C7/1045 , G11C7/1072 , G11C7/222 , G11C7/225 , G11C2207/2281
摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.
摘要翻译：能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于灭活信号在预充电循环中工作。

5. 发明授权

US5835956A Synchronous dram having a plurality of latency modes 失效
标题翻译：具有多个等待时间模式的同步电话
公开(公告)号：US5835956A
公开(公告)日：1998-11-10
申请号：US822148
申请日：1997-03-17
申请人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
发明人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/4076 , G11C11/408 , G11C11/409 , G06F13/16
CPC分类号： G11C7/1018 , G11C11/406 , G11C11/40618 , G11C11/4076 , G11C11/408 , G11C11/4082 , G11C11/4087 , G11C7/1045 , G11C7/1072 , G11C7/222 , G11C7/225 , G11C2207/2281
摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.
摘要翻译：能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于灭活信号在预充电循环中工作。

6. 发明授权

US5703828A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5703828A
公开(公告)日：1997-12-30
申请号：US580622
申请日：1995-12-29
申请人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
发明人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/4076 , G11C11/408 , G11C11/409 , G11C8/00
CPC分类号： G11C7/1018 , G11C11/406 , G11C11/40618 , G11C11/4076 , G11C11/408 , G11C11/4082 , G11C11/4087 , G11C7/1045 , G11C7/1072 , G11C7/222 , G11C7/225 , G11C2207/2281
摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.
摘要翻译：能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于灭活信号在预充电循环中工作。

7. 发明授权

US5822270A Circuit for generating internal column address suitable for burst mode 失效
标题翻译：产生适用于突发模式的内部列地址的电路
公开(公告)号：US5822270A
公开(公告)日：1998-10-13
申请号：US769434
申请日：1996-12-19
申请人： Churoo Park
发明人： Churoo Park
IPC分类号： G11C11/408 , G11C7/10 , G11C11/407 , G11C8/00
CPC分类号： G11C7/1018 , G11C7/1072
摘要： An internal column address generation circuit generates an internal column address by utilizing an asynchronous counter. The circuit includes a column address buffer for synchronizing an initially received external address with an external system clock to generate the internal column address, and for synchronizing a counting bit output signal received at an internal input node with the external system clock to generate the internal column address; and an asynchronous counter connected to an output node of the column address buffer, for generating the bit output signal having the same or opposite phase as/to a phase of the internal column address received from the column address buffer, in response to a carry generation state.
摘要翻译：内部列地址生成电路利用异步计数器生成内部列地址。该电路包括列地址缓冲器，用于使初始接收到的外部地址与外部系统时钟同步以产生内部列地址，并且用于使在内部输入节点处接收的计数位输出信号与外部系统时钟同步以产生内部列地址; 以及连接到列地址缓冲器的输出节点的异步计数器，用于响应于进位生成，产生与列地址缓冲器接收的内部列地址的相位相同或相反相位的位输出信号州。

8. 发明授权

US5631871A System for selecting one of a plurality of memory banks for use in an active cycle and all other banks for an inactive precharge cycle 失效
标题翻译：用于选择在活动周期中使用的多个存储体组中的一个并用于无效预充电循环的所有其它存储体的系统
公开(公告)号：US5631871A
公开(公告)日：1997-05-20
申请号：US578151
申请日：1995-12-29
申请人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
发明人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/4076 , G11C11/408 , G11C11/409 , B01F7/00 , B01F13/00
CPC分类号： G11C7/1018 , G11C11/406 , G11C11/40618 , G11C11/4076 , G11C11/408 , G11C11/4082 , G11C11/4087 , G11C7/1045 , G11C7/1072 , G11C7/222 , G11C7/225 , G11C2207/2281
摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.
摘要翻译：能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于灭活信号在预充电循环中工作。

9. 发明授权

US5621691A Column redundancy circuit and method of semiconductor memory device 失效
标题翻译：半导体存储器件的列冗余电路和方法
公开(公告)号：US5621691A
公开(公告)日：1997-04-15
申请号：US518863
申请日：1995-08-24
申请人： Churoo Park
发明人： Churoo Park
IPC分类号： G11C29/00 , G11C29/04 , G11C7/00 , G11C8/00 , G11C17/00
CPC分类号： G11C29/802 , G11C29/806
摘要： A column redundancy circuit and method of a semiconductor memory device. The column redundancy circuit comprises a programming element for programming a repair column address; a comparing element for comparing the programmed repair column address with a column address inputted from outside to thereby generate a redundancy enable control signal according to result of the comparison; a decoding element for decoding the repair column address signal to thereby generate a decoding signal; and a redundancy column select element for compounding the decoding signal and a data input signal to thereby enable a redundancy column select signal.
摘要翻译：半导体存储器件的列冗余电路和方法。列冗余电路包括用于编程修复列地址的编程元件; 比较元件，用于将编程的修复列地址与从外部输入的列地址进行比较，从而根据比较结果生成冗余使能控制信号; 解码单元，用于对修复列地址信号进行解码，从而生成解码信号; 以及用于使解码信号和数据输入信号复合的冗余列选择元件，从而使能冗余列选择信号。

10. 发明授权

US5933379A Method and circuit for testing a semiconductor memory device operating at high frequency 失效
标题翻译：用于测试高频工作的半导体存储器件的方法和电路
公开(公告)号：US5933379A
公开(公告)日：1999-08-03
申请号：US52053
申请日：1998-03-30
申请人： Churoo Park , Soo-In Cho
发明人： Churoo Park , Soo-In Cho
IPC分类号： G11C29/50 , G11C29/56 , G11C7/00
CPC分类号： G11C29/50 , G11C29/56 , G11C11/401
摘要： A circuit for testing a semiconductor memory device comprises a latency controller for controlling the latency of the external clock signal, an internal column address generator for generating a column address signal in the memory device, and a mode register for generating a mode signal. The circuit for testing semiconductor memory devices also includes a column address decoder for decoding the output address signal of the internal column address generator, a memory cell for reading or writing data, an input/output control unit for controlling the data input/output of the memory cell according to the output signal of the latency controller, a data input buffer, and a data output buffer. Further provided are a frequency multiplier for generating an internal clock signal having a frequency "n" times the frequency of the external clock signal. By providing the above-mentioned improvements, the conventional test equipment can be used to test high frequency memory devices.
摘要翻译：用于测试半导体存储器件的电路包括用于控制外部时钟信号的等待时间的等待时间控制器，用于在存储器件中产生列地址信号的内部列地址发生器和用于产生模式信号的模式寄存器。用于测试半导体存储器件的电路还包括用于解码内部列地址发生器的输出地址信号的列地址解码器，用于读取或写入数据的存储单元，用于控制数据输入/输出的输入/输出控制单元存储单元根据等待时间控制器的输出信号，数据输入缓冲器和数据输出缓冲器。还提供了一种用于产生具有外部时钟信号频率“n”倍的内部时钟信号的倍频器。通过提供上述改进，常规测试设备可用于测试高频存储器件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式