专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5923612A Synchronous semiconductor memory device having macro command storage and execution method therefor 失效
标题翻译：具有宏命令存储及其执行方法的同步半导体存储器件
公开(公告)号：US5923612A
公开(公告)日：1999-07-13
申请号：US928595
申请日：1997-09-12
申请人： Chul Woo Park , Myung-Chan Choi
发明人： Chul Woo Park , Myung-Chan Choi
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F12/02 , G11C11/401 , G11C11/407 , G11C8/00
CPC分类号： G06F9/3836 , G06F9/3017 , G06F9/3802 , G06F9/3869
摘要： A semiconductor memory device having a macro command function includes a macro storage section for storing a series of external instructions synchronized with a clock signal and a plurality of interval data corresponding to a number of clock pulses occurring between the external instructions. A counter is also included for counting the clock pulses and for producing an output representing a number of clock pulses occurring since an initialization of the counter, and a selecting section is included for selecting between a current external instruction synchronized with the clock signal and the external instructions read out from the macro storage section. A comparing section is included for comparing the interval data of the appropriate external instruction from the macro storage section with an output of the counter, and a macro control section is included for controlling the macro storage section in response to a macro store command so that the series of external instructions and the number of clock pulses counted by the counter are stored in the macro storage section. The macro control means also controlling the selecting section to select the macro storage section in response to a macro execute command so that the series of instructions stored in the macro storage section are sequentially read out. The macro control also produces a next command when the interval data of the read-out external instruction equals the output of the counter.
摘要翻译：具有宏指令功能的半导体存储器件包括宏存储部分，用于存储与时钟信号同步的一系列外部指令以及对应于外部指令之间出现的时钟脉冲数的多个间隔数据。还包括计数器，用于对时钟脉冲进行计数，并产生表示自计数器初始化以来出现的时钟脉冲数的输出，并且包括选择部分，用于在与时钟信号同步的当前外部指令和外部指令从宏存储部分读出。包括比较部分，用于将来自宏存储部分的适当的外部指令的间隔数据与计数器的输出进行比较，并且包括宏控制部分，用于响应于宏存储命令来控制宏存储部分，一系列外部指令和计数器计数的时钟脉冲数存储在宏存储部分中。宏控制装置还响应宏执行命令控制选择部分选择宏存储部分，以便顺序地读出存储在宏存储部分中的一系列指令。当读出的外部指令的间隔数据等于计数器的输出时，宏控制也产生下一个命令。

2. 发明授权

US08238148B2 Semiconductor device having architecture for reducing area and semiconductor system including the same 有权
标题翻译：具有用于减小面积的结构的半导体器件和包括其的半导体系统
公开(公告)号：US08238148B2
公开(公告)日：2012-08-07
申请号：US12652190
申请日：2010-01-05
申请人： Ho Jung Kim , Chul Woo Park , Sang Beom Kang , Jung Min Lee , Hyun Ho Choi
发明人： Ho Jung Kim , Chul Woo Park , Sang Beom Kang , Jung Min Lee , Hyun Ho Choi
IPC分类号： G11C11/00 , G11C7/10 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1039 , G11C7/1033 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C13/0004 , G11C2207/107
摘要： A semiconductor device having an architecture for reducing an area is provided. The semiconductor device includes a memory cell array including a plurality of non-volatile memory cells, a plurality of registers each configured to store pre-fetch unit data, and a write driver circuit configured to write pre-fetch unit data sequentially output from the plurality of registers to the memory cell array during a write operation. The semiconductor device also includes a sense amplifier circuit configured to sense and amplify pre-fetch unit data sequentially output from the memory cell array and to sequentially store the amplified pre-fetch unit data in the plurality of registers, respectively, during a read operation.
摘要翻译：提供了具有用于减小面积的架构的半导体器件。半导体器件包括存储单元阵列，该存储单元阵列包括多个非易失性存储器单元，多个寄存器，每个寄存器被配置为存储预取单元数据;以及写入驱动器电路，被配置为写入从多个单元顺序地输出的预取单元数据的寄存器在写操作期间到存储单元阵列。半导体器件还包括读出放大器电路，其被配置为感测并放大从存储单元阵列顺序输出的预取单元数据，并且在读取操作期间分别顺序地将放大的预取单元数据存储在多个寄存器中。

3. 发明授权

US07837120B1 Modular memory card and method of making same 有权
标题翻译：模块化存储卡及其制作方法
公开(公告)号：US07837120B1
公开(公告)日：2010-11-23
申请号：US11288906
申请日：2005-11-29
申请人： Sang Jae Jang , Chul Woo Park , Choon Heung Lee
发明人： Sang Jae Jang , Chul Woo Park , Choon Heung Lee
IPC分类号： G06K19/06
CPC分类号： G06K19/07732
摘要： In accordance with the present invention, there is provided multiple embodiments of a memory card, each embodiment including a module comprising at least a printed circuit board having an electronic circuit device mounted thereto. The module is inserted into a complementary cavity formed within a case of the memory card, such case generally defining the outer appearance of the memory card. The module is secured within the cavity of the case through the use of an adhesive. In each embodiment of the present invention, the module is uniquely configured to prevent adhesive leakage from within the corresponding cavity of the case of the memory card when the module is secured within the cavity.
摘要翻译：根据本发明，提供了存储卡的多个实施例，每个实施例包括至少包括安装有电子电路装置的印刷电路板的模块。模块被插入形成在存储卡的壳体内的互补空腔中，这种情况通常限定存储卡的外观。模块通过使用粘合剂固定在外壳的腔内。在本发明的每个实施例中，模块被独特地构造成当模块固定在空腔内时，防止粘合剂从存储卡的壳体的相应空腔内泄漏。

4. 发明申请

US20100284216A1 INFORMATION STORAGE DEVICES USING MAGNETIC DOMAIN WALL MOVEMENT AND METHODS OF OPERATING THE SAME 有权
标题翻译：使用磁畴壁移动的信息存储设备及其操作方法
公开(公告)号：US20100284216A1
公开(公告)日：2010-11-11
申请号：US12775160
申请日：2010-05-06
申请人： Ho Jung Kim , Sang Beom Kang , Chul Woo Park , Hyun Ho Choi , Jong Wan Kim , Young Pill Kim , Sung Chul Lee
发明人： Ho Jung Kim , Sang Beom Kang , Chul Woo Park , Hyun Ho Choi , Jong Wan Kim , Young Pill Kim , Sung Chul Lee
IPC分类号： G11C11/14 , G11C7/00 , G11C8/00
CPC分类号： G11C11/1653 , G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： An information storage device includes a first portion comprising at first at least one magnetic track, each of the at least one magnetic track in the first portion including a first plurality of magnetic domains and being configured to store a first type of data therein and a second portion comprising a second at least one magnetic track, each of the at least one magnetic track in the second portion including a second plurality of magnetic domains and being configured to store a second type of data therein, the second type of data being related to the first type of data.
摘要翻译：信息存储装置包括第一部分，其首先包括至少一个磁道，第一部分中的至少一个磁道中的每一个包括第一多个磁畴，并且被配置为在其中存储第一类型的数据，部分包括第二至少一个磁道，第二部分中的至少一个磁道中的每一个包括第二多个磁畴，并且被配置为在其中存储第二类型的数据，第二类型的数据与第一类数据。

5. 发明申请

US20100226165A1 RESISTIVE MEMORY DEVICES HAVING A STACKED STRUCTURE AND METHODS OF OPERATION THEREOF 有权
标题翻译：具有堆叠结构的电阻式存储器件及其操作方法
公开(公告)号：US20100226165A1
公开(公告)日：2010-09-09
申请号：US12714950
申请日：2010-03-01
申请人： Sang Beom Kang , Chul Woo Park , Hyun Ho Choi , Ho Jung Kim
发明人： Sang Beom Kang , Chul Woo Park , Hyun Ho Choi , Ho Jung Kim
IPC分类号： G11C11/00 , G11C8/08 , G11C7/00
CPC分类号： G11C7/1045 , G11C5/02 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2211/5641 , G11C2213/71 , G11C2213/72 , G11C2213/79
摘要： A memory device includes a stacked resistive memory cell array comprising a plurality of resistive memory cell layers stacked on a semiconductor substrate, wherein respective memory cell layers are configured to store data according to respective program modes comprising a number of bits per cell. The memory device further includes a control circuit configured to identify a program mode of a selected memory cell layer responsive to an address signal and to access the selected memory cell layer responsive to the address signal according to the identified program mode. The program modes may include a single-level cell mode and at least one multi-level cell mode.
摘要翻译：存储器件包括堆叠在半导体衬底上的多个电阻存储器单元层的堆叠电阻性存储单元阵列，其中相应的存储单元层被配置为根据包括每个单元的位数的各自的程序模式来存储数据。该存储装置还包括控制电路，该控制电路被配置为响应于地址信号来识别所选择的存储器单元层的编程模式，并且根据所识别的程序模式响应于地址信号访问所选择的存储单元层。程序模式可以包括单级单元模式和至少一个多级单元模式。

6. 发明申请

US20090021921A1 Memory card and its manufacturing method 审中-公开
标题翻译：存储卡及其制造方法
公开(公告)号：US20090021921A1
公开(公告)日：2009-01-22
申请号：US11114342
申请日：2005-04-26
申请人： Sang Jae Jang , Chul Woo Park , Suk Ku Ko , Choon Heung Lee
发明人： Sang Jae Jang , Chul Woo Park , Suk Ku Ko , Choon Heung Lee
IPC分类号： H05K1/14
CPC分类号： H05K3/284 , H01L23/3121 , H01L23/3135 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/32225 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/49109 , H01L2224/73265 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H05K1/0266 , H05K1/117 , H05K3/0052 , H05K2201/09145 , H05K2201/0989 , H05K2201/10159 , H05K2203/0191 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A memory card comprising a circuit board having opposed upper and lower circuit board surfaces, multiple side edges, a chamfer extending between a pair of the side edges, a plurality of pads disposed on the lower circuit board surface, and a conductive pattern which is disposed on the upper circuit board surface and electrically connected to the pads. At least one electronic circuit device is attached to the upper circuit board surface and electrically connected to the conductive pattern of the circuit board. A body at least partially encapsulates the circuit board and the electronic circuit element such that a section of the upper circuit board surface extending along the entirety of the chamfer is not covered by the body.
摘要翻译：一种存储卡，包括具有相对的上电路板表面和下电路板表面的电路板，多个侧边缘，在一对侧边缘之间延伸的倒角，设置在下电路板表面上的多个焊盘和设置在下电路板表面上的导电图案在上电路板表面上并电连接到焊盘。至少一个电子电路装置附接到上电路板表面并电连接到电路板的导电图案。主体至少部分地封装电路板和电子电路元件，使得沿整个倒角延伸的上部电路板表面的一部分不被主体覆盖。

7. 发明授权

US07359204B1 Multiple cover memory card 有权
标题翻译：多盖存储卡
公开(公告)号：US07359204B1
公开(公告)日：2008-04-15
申请号：US11355092
申请日：2006-02-15
申请人： Sang Jae Jang , Chul Woo Park , Jong Woon Choi , Jae Dong Kim , Choon Heung Lee , Chang Deok Lee
发明人： Sang Jae Jang , Chul Woo Park , Jong Woon Choi , Jae Dong Kim , Choon Heung Lee , Chang Deok Lee
IPC分类号： H05K7/20
CPC分类号： H05K5/0256 , G06K19/07 , G06K19/07732
摘要： A memory card including a module comprising at least a printed circuit board having an electronic circuit device mounted thereto and at least one I/O pad and at least one test pad disposed thereon. The module is inserted into a complementary cavity formed within a case of the memory card, such case generally defining the outer appearance of the memory card. The module is secured within the cavity of the case through the use of an adhesive. In each embodiment of the present invention, first and second covers are movably attached to a case for selectively covering or exposing the I/O pads and the test features/pads of the module of the memory card.
摘要翻译：一种存储卡，包括至少包括安装有电子电路装置的印刷电路板和至少一个I / O焊盘和至少一个设置在其上的测试焊盘的模块。模块被插入形成在存储卡的壳体内的互补空腔中，这种情况通常限定存储卡的外观。模块通过使用粘合剂固定在外壳的腔内。在本发明的每个实施例中，第一和第二盖可移动地附接到壳体，用于选择性地覆盖或暴露存储卡模块的I / O焊盘和测试特征/焊盘。

8. 发明授权

US08369173B2 Semiconductor devices and methods for changing operating characteristics and semiconductor systems including the same 有权
标题翻译：用于改变工作特性的半导体器件和方法以及包括其的半导体系统
公开(公告)号：US08369173B2
公开(公告)日：2013-02-05
申请号：US12706756
申请日：2010-02-17
申请人： Ho Jung Kim , Chul Woo Park , Sang Beom Kang , Hyun Ho Choi , Jung Min Lee , Seung Eon Ahn
发明人： Ho Jung Kim , Chul Woo Park , Sang Beom Kang , Hyun Ho Choi , Jung Min Lee , Seung Eon Ahn
IPC分类号： G11C7/00
CPC分类号： G11C5/14 , G11C5/147 , G11C7/22 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/20 , G11C29/02 , G11C29/021 , G11C29/023 , G11C29/028 , G11C2029/4402 , G11C2207/2254
摘要： A method of changing a parameter in a semiconductor device is provided. The method includes receiving and storing data in a storage region; and changing at least one between a DC characteristic and an AC timing characteristic of a parameter, used to access a non-volatile memory cell included in a memory core of the semiconductor device, according to the data stored in the storage.
摘要翻译：提供了一种改变半导体器件中的参数的方法。该方法包括在存储区域中接收和存储数据; 以及根据存储在存储器中的数据，在用于访问包括在半导体器件的存储器核心中的非易失性存储单元的参数的DC特性和AC定时特性之间改变至少一个。

9. 发明申请

US20120063196A1 RESISTIVE MEMORY DEVICE AND METHOD OF CONTROLLING REFRESH OPERATION OF RESISTIVE MEMORY DEVICE 有权
标题翻译：电阻式存储器件及其控制电阻式存储器件的刷新操作的方法
公开(公告)号：US20120063196A1
公开(公告)日：2012-03-15
申请号：US13231998
申请日：2011-09-14
申请人： Ho Jung Kim , Sang Beom Kang , Hong Sun Hwang , Chul Woo Park
发明人： Ho Jung Kim , Sang Beom Kang , Hong Sun Hwang , Chul Woo Park
IPC分类号： G11C11/00
CPC分类号： G11C29/021 , G11C13/00 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C13/004 , G11C16/3418 , G11C2013/0057 , G11C2013/0076
摘要： A resistive memory device comprises a memory cell array comprising a plurality of memory units. The memory device performs a refresh read operation to check a condition of each of the memory units. Then, it determines whether to refresh each memory unit based on data read by performing the refresh read operation, and refreshes the memory unit according to a result of the determination. The refresh read operation uses a reference resistance with a smaller margin from a resistance distribution than a normal read operation.
摘要翻译：电阻式存储器件包括包括多个存储单元的存储单元阵列。存储器件执行刷新读取操作以检查每个存储器单元的状况。然后，基于通过执行刷新读取操作读取的数据来确定是否刷新每个存储器单元，并且根据确定的结果来刷新存储器单元。刷新读取操作使用具有比正常读取操作更小的电阻分布的参考电阻。

10. 发明授权

US08031517B2 Memory device, memory system having the same, and programming method of a memory cell 有权
标题翻译：存储器件，具有相同的存储器系统以及存储器单元的编程方法
公开(公告)号：US08031517B2
公开(公告)日：2011-10-04
申请号：US12461036
申请日：2009-07-30
申请人： Ho Jung Kim , Chul Woo Park , Sang Beom Kang , Hyun Ho Choi , Seung Eon Ahn
发明人： Ho Jung Kim , Chul Woo Park , Sang Beom Kang , Hyun Ho Choi , Seung Eon Ahn
IPC分类号： G11C11/00
CPC分类号： G11C11/56 , G11C8/06 , G11C8/10 , G11C11/5678 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2013/0092
摘要： A method of writing multi-bit data to a semiconductor memory device with memory cells storing data defined by a threshold value, the method comprising, for each memory cell, writing a least significant bit, verifying completion of writing the least significant bit, verifying including comparing a written value to one of a low least significant bit verification value and a high least significant bit verification value, and writing a next significant bit upon completion of writing the least significant bit.
摘要翻译：一种将多位数据写入半导体存储器件的方法，其中存储单元存储由阈值定义的数据，该方法包括针对每个存储器单元写入最低有效位，验证写入最低有效位的完成，验证包括将写入值与低最低有效位验证值和高最低有效位验证值之一进行比较，以及在完成写入最低有效位时写入下一个有效位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式