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1. 发明授权

US07929367B2 Low power memory control circuits and methods 失效
标题翻译：低功耗存储器控制电路及方法
公开(公告)号：US07929367B2
公开(公告)日：2011-04-19
申请号：US11534609
申请日：2006-09-22
申请人： Seung-Moon Yoo , Myung Chan Choi , Young Tae Kim , Sung Ju Son , Sang-Kyun Han , Sun Hyoung Lee
发明人： Seung-Moon Yoo , Myung Chan Choi , Young Tae Kim , Sung Ju Son , Sang-Kyun Han , Sun Hyoung Lee
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C11/4091 , G11C7/065 , G11C7/08 , G11C7/20 , G11C8/08 , G11C8/10 , G11C8/12 , G11C8/14 , G11C11/406 , G11C11/4072 , G11C11/4074 , G11C11/4085 , G11C11/4087 , G11C2207/065 , G11C2207/2227 , G11C2211/4068 , H01L27/0207 , H01L27/10897
摘要： Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the invention describes lowering refresh current. An aspect describes reducing the standby current. An aspect of the invention describes lowering leakage resulting from duplicated circuits, such as row decoders and word line drivers. An aspect describes methods of performing early wake-up of source transistors. A number of source transistor control mechanisms are taught. Circuit layouts methods are taught for optimizing integrated circuit layouts using the source transistors.
摘要翻译：描述用于抑制集成电路漏电流的电路和方法。这些电路和方法中的许多特别适用于动态存储器电路。示例描述了用于产生虚拟电压的电源，接地或两者以及电源和接地源晶体管的使用。本发明的一个方面描述降低刷新电流。一方面描述了减少待机电流。本发明的一个方面描述了降低由诸如行解码器和字线驱动器的复制电路产生的泄漏。一方面描述了执行源晶体管的早期唤醒的方法。教授了许多源晶体管控制机制。教导了使用源极晶体管优化集成电路布局的电路布局方法。

2. 发明申请

US20070081405A1 LOW POWER MEMORY CONTROL CIRCUITS AND METHODS 失效
标题翻译：低功率存储器控制电路和方法
公开(公告)号：US20070081405A1
公开(公告)日：2007-04-12
申请号：US11534609
申请日：2006-09-22
申请人： Seung-Moon Yoo , Myung Chan Choi , Young Tae Kim , Sung Ju Son , Sang-Kyun Han , Sun Hyoung Lee
发明人： Seung-Moon Yoo , Myung Chan Choi , Young Tae Kim , Sung Ju Son , Sang-Kyun Han , Sun Hyoung Lee
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C7/065 , G11C7/08 , G11C7/20 , G11C8/08 , G11C8/10 , G11C8/12 , G11C8/14 , G11C11/406 , G11C11/4072 , G11C11/4074 , G11C11/4085 , G11C11/4087 , G11C2207/065 , G11C2207/2227 , G11C2211/4068 , H01L27/0207 , H01L27/10897
摘要： Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the invention describes lowering refresh current. An aspect describes reducing the standby current. An aspect of the invention describes lowering leakage resulting from duplicated circuits, such as row decoders and word line drivers. An aspect describes methods of performing early wake-up of source transistors. A number of source transistor control mechanisms are taught. Circuit layouts methods are taught for optimizing integrated circuit layouts using the source transistors.
摘要翻译：描述用于抑制集成电路漏电流的电路和方法。这些电路和方法中的许多特别适用于动态存储器电路。示例描述了用于产生虚拟电压的电源，接地或两者以及电源和接地源晶体管的使用。本发明的一个方面描述降低刷新电流。一方面描述了减少待机电流。本发明的一个方面描述了降低由诸如行解码器和字线驱动器的复制电路产生的泄漏。一方面描述了执行源晶体管的早期唤醒的方法。教授了许多源晶体管控制机制。教导了使用源极晶体管优化集成电路布局的电路布局方法。

3. 发明授权

US07705625B2 Source transistor configurations and control methods 失效
标题翻译：源晶体管配置和控制方法
公开(公告)号：US07705625B2
公开(公告)日：2010-04-27
申请号：US11483263
申请日：2006-07-06
申请人： Seung-Moon Yoo , Jae Hoon Yoo , Jeongduk Sohn , Sung Ju Son , Myung Chan Choi , Young Tae Kim , Oh Sang Yoon , Sang-Kyun Han
发明人： Seung-Moon Yoo , Jae Hoon Yoo , Jeongduk Sohn , Sung Ju Son , Myung Chan Choi , Young Tae Kim , Oh Sang Yoon , Sang-Kyun Han
IPC分类号： H03K19/094
CPC分类号： H03K19/0016 , G11C7/1045 , G11C11/4074 , G11C11/4076 , G11C2207/2227
摘要： Source transistor configurations are described for reducing leakage and delay within integrated circuits. Virtual power and ground nodes are supported with the use of stacked transistor configurations, such as a two transistor stack between a first virtual supply connection and VSS, and a second virtual supply connection and VDD. Gate drives of these stacked transistors are modulated with different voltage levels in response to the operating power mode of the circuit, for example active mode, active-standby mode, and deep power-down mode. Means for driving these source stacks are described. In one embodiment separate virtual nodes are adapted for different types of circuits, such as buffers, row address strobe, and column address strobe. Other techniques, such as directional placement of the transistors is also described.
摘要翻译：源晶体管配置被描述为减少集成电路内的泄漏和延迟。使用堆叠晶体管配置（例如在第一虚拟电源连接和VSS之间的两个晶体管堆叠）和第二虚拟电源连接和VDD之间来支持虚拟电源和接地节点。这些堆叠晶体管的栅极驱动器响应于电路的工作功率模式，例如主动模式，主动待机模式和深度掉电模式，以不同的电压电平进行调制。描述了用于驱动这些源堆栈的装置。在一个实施例中，单独的虚拟节点适用于不同类型的电路，例如缓冲器，行地址选通和列地址选通。还描述了诸如晶体管的定向放置的其它技术。

4. 发明申请

US20120201085A1 LOW POWER MEMORY CONTROL CIRCUITS AND METHODS 审中-公开
标题翻译：低功率存储器控制电路和方法
公开(公告)号：US20120201085A1
公开(公告)日：2012-08-09
申请号：US13089486
申请日：2011-04-19
申请人： Seung-Moon Yoo , Myung Chan Choi , Young Tae Kim , Jung Ju Son , Sang-Kyun Han , Sun Hyoung Lee
发明人： Seung-Moon Yoo , Myung Chan Choi , Young Tae Kim , Jung Ju Son , Sang-Kyun Han , Sun Hyoung Lee
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C11/4091 , G11C7/065 , G11C7/08 , G11C7/20 , G11C8/08 , G11C8/10 , G11C8/12 , G11C8/14 , G11C11/406 , G11C11/4072 , G11C11/4074 , G11C11/4085 , G11C11/4087 , G11C2207/065 , G11C2207/2227 , G11C2211/4068 , H01L27/0207 , H01L27/10897
摘要： Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the invention describes lowering refresh current. An aspect describes reducing the standby current. An aspect of the invention describes lowering leakage resulting from duplicated circuits, such as row decoders and word line drivers. An aspect describes methods of performing early wake-up of source transistors. A number of source transistor control mechanisms are taught. Circuit layouts methods are taught for optimizing integrated circuit layouts using the source transistors.
摘要翻译：描述用于抑制集成电路漏电流的电路和方法。这些电路和方法中的许多特别适用于动态存储器电路。示例描述了用于产生虚拟电压的电源，接地或两者以及电源和接地源晶体管的使用。本发明的一个方面描述降低刷新电流。一方面描述了减少待机电流。本发明的一个方面描述了降低由诸如行解码器和字线驱动器的复制电路产生的泄漏。一方面描述了执行源晶体管的早期唤醒的方法。教授了许多源晶体管控制机制。教导了使用源极晶体管优化集成电路布局的电路布局方法。

5. 发明授权

US09833593B2 Catheter for treating ectopic pregnancy, catheter guide, and catheter unit for treating ectopic pregnancy, including the catheter and the catheter guide 有权
公开(公告)号：US09833593B2
公开(公告)日：2017-12-05
申请号：US13982928
申请日：2011-11-25
申请人： Sun Haeng Kim , Young Tae Kim , Ki Hoon Ahn
发明人： Sun Haeng Kim , Young Tae Kim , Ki Hoon Ahn
IPC分类号： A61M25/00 , A61B17/42 , A61M31/00 , A61M25/01 , A61B17/00 , A61B17/34 , A61B17/435
CPC分类号： A61M25/0026 , A61B17/3478 , A61B17/42 , A61B17/435 , A61B2017/00318 , A61B2017/00323 , A61B2017/00867 , A61M25/0032 , A61M25/007 , A61M25/01 , A61M31/00 , A61M2025/0031 , A61M2025/0037
摘要： The present invention relates to a catheter for treating ectopic pregnancy, of which one end is inserted into the fallopian tube through the vaginal cavity, and the other end is exposed to the outside of the body, wherein the catheter comprises: at least one passage portion forming a liquid passage entering through the one end or the other end; a penetrative portion connected to the one end, and including a foremost end for penetrating the gestational sac; and a connecting portion connected to the other end, and capable of being coupled to at least one syringe tool for injecting or suctioning the liquid. Accordingly, side effects from open surgery can be prevented, and excellent treatment effects can be obtained by more safely and quickly treating ectopic pregnancy.

6. 发明授权

US08454237B2 Spindle motor 失效
标题翻译：主轴电机
公开(公告)号：US08454237B2
公开(公告)日：2013-06-04
申请号：US12874103
申请日：2010-09-01
申请人： Young Tae Kim
发明人： Young Tae Kim
IPC分类号： F16C32/06
CPC分类号： F16C17/026 , F16C17/246
摘要： The spindle motor includes a rotating shaft and a sleeve. The rotating shaft has a stepped portion in a fluid dynamic pressure shafting system. The sleeve is fitted over the circumferential outer surface of the rotating shaft. A sleeve recess is formed in the inner surface of the sleeve so that the edges of the stepped portion are spaced apart from the sleeve.
摘要翻译：主轴电机包括旋转轴和套筒。旋转轴在流体动压轴系中具有台阶部分。套筒安装在旋转轴的圆周外表面上。套筒凹部形成在套筒的内表面中，使得阶梯部分的边缘与套筒间隔开。

7. 发明授权

US08230599B2 Method of manufacturing hydrodynamic bearing 失效
标题翻译：制造流体动力轴承的方法
公开(公告)号：US08230599B2
公开(公告)日：2012-07-31
申请号：US12285879
申请日：2008-10-15
申请人： Young Tae Kim , Jin San Kim , Young Hwan Lim , Il Oung Park , Ta Kyoung Lee
发明人： Young Tae Kim , Jin San Kim , Young Hwan Lim , Il Oung Park , Ta Kyoung Lee
IPC分类号： B21D53/10 , B23H3/00
CPC分类号： B21D53/10 , F16C17/02 , F16C17/026 , F16C33/14 , F16C2220/20 , F16C2220/66 , F16C2220/68 , F16C2223/04 , Y10T29/49639 , Y10T29/49702 , Y10T29/49707 , Y10T29/49709
摘要： Disclosed herein is a method of manufacturing a hydrodynamic bearing in which a metal bearing made of sintered metal powder is internally subjected to chemical etching, to form hydrodynamic pressure grooves thereon, thus assuring a high-precision and reliable hydrodynamic bearing. The method includes: compressing metal powder that is a raw material of the bearing in a press unit, and sintering the compressed metal powder at a predetermined temperature, thus preparing a sintered bearing; removing foreign substances adhering to the sintered bearing through a deburring process, and pressing the sintered bearing into a desired shape; forming a hydrodynamic groove, configured to generate hydrodynamic pressure, on an internal surface of the shaped bearing using chemical etching; and conducting a post treatment of cleaning the bearing including the hydrodynamic grooves thereon and drying the bearing.
摘要翻译：本文公开了一种制造流体动力轴承的方法，其中由烧结金属粉末制成的金属轴承在内部进行化学蚀刻，以在其上形成流体动力学压力槽，从而确保高精度和可靠的流体动力轴承。该方法包括：在压制单元中压制作为轴承原料的金属粉末，并在预定温度下烧结压缩的金属粉末，从而制备烧结轴承; 通过去毛刺处理去除附着在烧结轴承上的异物，将烧结后的轴承压制成所希望的形状; 使用化学蚀刻形成在所述成形轴承的内表面上产生流体动力学压力的流体动力槽; 并对其上包括流体动力槽的轴承进行清洗，并干燥轴承。

8. 发明授权

US08088703B2 Dielectric composition and ceramic electronic component manufactured therefrom 有权
标题翻译：介电组合物和由其制造的陶瓷电子部件
公开(公告)号：US08088703B2
公开(公告)日：2012-01-03
申请号：US12239288
申请日：2008-09-26
申请人： Sung Hyung Kang , Young Tae Kim , Kang Heon Hur , Jeong Oh Hong , Su Jin Kim
发明人： Sung Hyung Kang , Young Tae Kim , Kang Heon Hur , Jeong Oh Hong , Su Jin Kim
IPC分类号： C04B35/468
CPC分类号： C04B35/468 , C04B2235/3203 , C04B2235/3206 , C04B2235/3208 , C04B2235/3213 , C04B2235/3215 , C04B2235/3217 , C04B2235/3224 , C04B2235/3225 , C04B2235/3227 , C04B2235/3229 , C04B2235/3239 , C04B2235/3241 , C04B2235/3244 , C04B2235/3251 , C04B2235/3262 , C04B2235/3272 , C04B2235/3275 , C04B2235/3279 , C04B2235/3418 , C04B2235/3817 , C04B2235/3839 , C04B2235/5409 , C04B2235/6025 , C04B2235/79
摘要： Provided are a dielectric composition and a ceramic electronic component including the same. The dielectric composition includes (a) barium titanate having a specific surface area of 2.5 m2/g to 6.0 m2/g; (b) a mixture containing at least one or more materials selected from the group consisting of any one oxide of Mg, Ca, Sr, Ba and Zr, and any one carbonate thereof; (c) oxide containing at least one or more materials selected from the group consisting of Sc, Y, La, Ac, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu; (d) oxide containing at least one or more material selected from the group consisting of Cr, Mn, Fe, Co, and Ni; (e) oxide containing at least one or more material selected from the group consisting of V, Nb, and Ta; and (f) oxide containing at least one or more material selected from the group consisting of Si and Al. The dielectric composition can satisfy X8R characteristic, can be sintered at a low temperature, and can obtain high reliability.
摘要翻译：提供了一种电介质组合物和包括其的陶瓷电子部件。电介质组合物包括（a）比表面积为2.5m 2 / g至6.0m 2 / g的钛酸钡; （b）含有选自Mg，Ca，Sr，Ba和Zr的任何一种氧化物中的至少一种或多种的混合物及其任何一种碳酸酯的混合物; （c）含有选自Sc，Y，La，Ac，Ce，Pr，Nd，Pm，Sm，Eu，Gd，Tb，Dy，Ho，Er，Tm，Yb中的至少一种以上的材料的氧化物，卢; （d）含有选自Cr，Mn，Fe，Co和Ni中的至少一种或多种材料的氧化物; （e）含有选自V，Nb和Ta中的至少一种或多种材料的氧化物; 和（f）含有选自Si和Al的至少一种或多种材料的氧化物。电介质组成可满足X8R特性，可在低温烧结，可获得高可靠性。

9. 发明授权

US06295244B1 Semiconductor memory device and data read method thereof 有权
标题翻译：半导体存储器件及其数据读取方法
公开(公告)号：US06295244B1
公开(公告)日：2001-09-25
申请号：US09617524
申请日：2000-07-17
申请人： Young Tae Kim , Deok Joon Shin
发明人： Young Tae Kim , Deok Joon Shin
IPC分类号： G11C800
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C2207/2281
摘要： The present invention discloses a semiconductor memory device. The device includes a plurality of memory cell array blocks; a predetermined number of main buffers for resetting a predetermined number of pairs of main data lines corresponding to a predetermined number of pairs of data items output from each of the plurality of memory cell array blocks in response to a main buffer control signal, and for generating a predetermined number of pairs of data when the data of each of the predetermined number of pairs of main data lines become complementary levels, the predetermined number of pair of data being reset after a lapse of predetermined time; a predetermined number of data output buffers for respectively receiving and buffering the predetermined number of pairs of data items generated by the predetermined number of main buffers, in response to a data output buffer control signal; and data output buffer control signal generating means for generating the data output buffer control signal, the data output buffer control signal being enabled in response to a control signal and disabled after a lapse of predetermined time from the point of time at which each of the pair of data items output from the predetermined number of main buffers reaches the desired complementary levels, thereby improving data read speed.
摘要翻译：本发明公开了一种半导体存储器件。该装置包括多个存储单元阵列块; 预定数量的主缓冲器，用于响应于主缓冲器控制信号来复位与从多个存储单元阵列块中的每一个输出的预定数量的数据对对应的预定数量的主数据线对，并且用于生成当预定数量的主数据线对中的每一个的数据成为互补电平时，预定数量的数据对，预定数量的数据对在经过预定时间之后被复位; 预定数量的数据输出缓冲器，用于响应于数据输出缓冲器控制信号分别接收和缓冲由预定数量的主缓冲器产生的预定数量的数据项对; 以及数据输出缓冲器控制信号产生装置，用于产生数据输出缓冲器控制信号，数据输出缓冲器控制信号响应于控制信号被使能，并且在从该对中的每一个的时间点起经过预定时间后被禁用从预定数量的主缓冲器输出的数据项达到期望的互补电平，从而提高数据读取速度。

10. 发明授权

US11958080B2 Parcel sorting system 有权
公开(公告)号：US11958080B2
公开(公告)日：2024-04-16
申请号：US17437818
申请日：2020-06-10
申请人： DAESUNG INDUSTRIAL CO., LTD , YOUNG CONSULTING LTD. , Young Tae Kim
发明人： Young Tae Kim
IPC分类号： B07C3/08 , B07C3/14 , B65G23/00 , B65G43/08 , B65G47/12 , B65G47/49
CPC分类号： B07C3/08 , B07C3/14 , B65G43/08 , B65G47/12 , B65G47/493 , B65G2203/0216 , B65G2203/0233 , B65G2203/041
摘要： The present invention relates to a parcel sorting system which is operated using two separate tracks so as to distinguish between concentrated population areas and other areas, and feed and sort only parcels destined for a corresponding area, whereby parcel sorting can be efficiently performed, and the system can be efficiently constructed while occupying a small area.

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