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    • 1. 发明申请
    • APPARATUS FOR CONTROLLING SENSITIVITY BY USING DIGITAL GATING IN RECEIVER AND RECEIVER WITH THE SAME
    • 通过在接收机中使用数字增益来控制灵敏度的装置和接收器的接收器
    • US20090316834A1
    • 2009-12-24
    • US12467627
    • 2009-05-18
    • Sangho ShinSang-Hyun ChoSeok-Oh YunJong-Moon Kim
    • Sangho ShinSang-Hyun ChoSeok-Oh YunJong-Moon Kim
    • H04L25/06H04B1/16H03D1/24
    • H04B1/28H04L25/06
    • Disclosed is a wireless communication system, more particularly, a receiver and a chipset for DSRC. A receiver includes: a low noise amplifier (LNA) amplifying a received radio (RF) signal while minimizing amplification of noise included in the received RF signal; a mixer down-converting a frequency of an output signal of the LNA to output an intermediate frequency (IF) signal; a frequency synthesizer generating and outputting a frequency signal for the frequency-down conversion of the mixer to the mixer; a bandpass filter passing a necessary band of a channel in an output signal of the mixer; a log amplifier amplifying an output signal of the bandpass filter in log scale and outputting a received signal strength indicator of an output signal of the bandpass filter; a detector comparing an output of the log amplifier with a predetermined binary threshold value, outputting a first binary signal when the output of the log amplifier is less than the predetermined binary threshold value, and outputting a second binary signal when the output of the log amplifier is equal to or greater than the predetermined binary threshold value; a switch serially connected with an output terminal of the detector; and a switch controller comparing the received signal strength indicator of the output signal of the log amplifier with an RSSI threshold, opening the switch when the received signal strength indicator is less than the RSSI threshold, and closing the switch when the received signal strength indicator is equal to or grater than the RSSI threshold.
    • 公开了一种无线通信系统,更具体地,用于DSRC的接收机和芯片组。 接收机包括:放大接收的无线电(RF)信号的低噪声放大器(LNA),同时最小化包含在所接收的RF信号中的噪声的放大; 混频器降频转换LNA的输出信号的频率以输出中频(IF)信号; 频率合成器,生成并输出用于混频器的降频转换的混频器的频率信号; 带通滤波器,在混频器的输出信号中通过通道的必要频带; 对数放大器,以对数标度放大带通滤波器的输出信号,并输出带通滤波器的输出信号的接收信号强度指示符; 将对数放大器的输出与预定的二进制阈值进行比较的检测器,当对数放大器的输出小于预定的二进制阈值时输出第一二进制信号,并且当对数放大器的输出输出时输出第二二进制信号 等于或大于预定二进制阈值; 与检测器的输出端子串联连接的开关; 以及开关控制器,将对数放大器的输出信号的接收信号强度指示符与RSSI阈值进行比较,当接收信号强度指示符小于RSSI阈值时打开开关,并且当接收信号强度指示符为 等于或大于RSSI阈值。
    • 3. 发明授权
    • Dynamic memory refresh configurations and leakage control methods
    • 动态内存刷新配置和泄漏控制方法
    • US07522464B2
    • 2009-04-21
    • US11779716
    • 2007-07-18
    • Seung-Moon YooMyung Chan ChoiSangho ShinSang-Kyun Han
    • Seung-Moon YooMyung Chan ChoiSangho ShinSang-Kyun Han
    • G11C7/00
    • G11C11/406G11C11/4094G11C29/783G11C29/83G11C29/832G11C2211/4061G11C2211/4065G11C2211/4067G11C2211/4068
    • Dynamic Random Access Memory (DRAM) circuits and methods are described for reducing leakage and increasing repaired yield. These objects are accomplished according to the invention by grouping refresh cycles within a single activation of power control, the use of limiting circuits or fuses to mitigate power losses associated with micro-bridging of bit-lines and word-lines, modulating the bit-line voltage at the end of precharge cycles, configuring refresh control circuits to use redundant word-lines in generating additional refresh cycles for redundant rows of memory cells, and combinations thereof. In one aspect, word-line fuses indicate modes of use as: unused, replacement, additional refresh, and replacement with additional refresh. The refresh control circuit utilizes these modes in combination with the X-address stored in the word-line fuses for controlling the generation of additional refresh cycles toward overcoming insufficient data retention intervals in select memory cell rows.
    • 描述了用于减少泄漏和提高修复产量的动态随机存取存储器(DRAM)电路和方法。 根据本发明,通过在功率控制的单个激活中分组刷新周期,使用限制电路或熔丝来减轻与位线和字线的微桥接相关联的功率损耗,调制位线 在预充电周期结束时配置刷新控制电路以使用冗余字线来产生冗余的存储器单元行的附加刷新周期,以及它们的组合。 在一个方面,字线保险丝将使用模式指示为:未使用,替换,附加刷新以及附加刷新的替换。 刷新控制电路利用这些模式与存储在字线保险丝中的X地址相组合,用于控制产生额外的刷新周期以克服选择存储单元行中的不充足的数据保留间隔。
    • 5. 发明授权
    • Apparatus for controlling sensitivity by using digital gating in receiver and receiver with the same
    • 用于通过在接收机和接收机中使用数字门控来控制灵敏度的装置
    • US08270538B2
    • 2012-09-18
    • US12467627
    • 2009-05-18
    • Sangho ShinSang-Hyun ChoSeok-Oh YunJong-Moon Kim
    • Sangho ShinSang-Hyun ChoSeok-Oh YunJong-Moon Kim
    • H03D1/24
    • H04B1/28H04L25/06
    • Disclosed is a wireless communication system, more particularly, a receiver and a chipset for DSRC. A receiver includes: a low noise amplifier (LNA) amplifying a received radio (RF) signal while minimizing amplification of noise included in the received RF signal; a mixer down-converting a frequency of an output signal of the LNA to output an intermediate frequency (IF) signal; a frequency synthesizer generating and outputting a frequency signal for the frequency-down conversion of the mixer to the mixer; a bandpass filter passing a necessary band of a channel in an output signal of the mixer; a log amplifier amplifying an output signal of the bandpass filter in log scale and outputting a received signal strength indicator of an output signal of the bandpass filter; a detector comparing an output of the log amplifier with a predetermined binary threshold value, outputting a first binary signal when the output of the log amplifier is less than the predetermined binary threshold value, and outputting a second binary signal when the output of the log amplifier is equal to or greater than the predetermined binary threshold value; a switch serially connected with an output terminal of the detector; and a switch controller comparing the received signal strength indicator of the output signal of the log amplifier with an RSSI threshold, opening the switch when the received signal strength indicator is less than the RSSI threshold, and closing the switch when the received signal strength indicator is equal to or grater than the RSSI threshold.
    • 公开了一种无线通信系统,更具体地,用于DSRC的接收机和芯片组。 接收机包括:放大接收的无线电(RF)信号的低噪声放大器(LNA),同时最小化包含在所接收的RF信号中的噪声的放大; 混频器降频转换LNA的输出信号的频率以输出中频(IF)信号; 频率合成器,生成并输出用于混频器的降频转换的混频器的频率信号; 带通滤波器,在混频器的输出信号中通过通道的必要频带; 对数放大器,以对数标度放大带通滤波器的输出信号,并输出带通滤波器的输出信号的接收信号强度指示符; 将对数放大器的输出与预定的二进制阈值进行比较的检测器,当对数放大器的输出小于预定的二进制阈值时输出第一二进制信号,并且当对数放大器的输出输出时输出第二二进制信号 等于或大于预定二进制阈值; 与检测器的输出端子串联连接的开关; 以及开关控制器,将对数放大器的输出信号的接收信号强度指示符与RSSI阈值进行比较,当接收信号强度指示符小于RSSI阈值时打开开关,并且当接收信号强度指示符为 等于或大于RSSI阈值。
    • 6. 发明申请
    • DYNAMIC MEMORY REFRESH CONFIGURATIONS AND LEAKAGE CONTROL METHODS
    • 动态记忆刷新配置和泄漏控制方法
    • US20080031068A1
    • 2008-02-07
    • US11779716
    • 2007-07-18
    • Seung-Moon YooMyung ChoiSangho ShinSang-Kyun Han
    • Seung-Moon YooMyung ChoiSangho ShinSang-Kyun Han
    • G11C7/00
    • G11C11/406G11C11/4094G11C29/783G11C29/83G11C29/832G11C2211/4061G11C2211/4065G11C2211/4067G11C2211/4068
    • Dynamic Random Access Memory (DRAM) circuits and methods are described for reducing leakage and increasing repaired yield. These objects are accomplished according to the invention by grouping refresh cycles within a single activation of power control, the use of limiting circuits or fuses to mitigate power losses associated with micro-bridging of bit-lines and word-lines, modulating the bit-line voltage at the end of precharge cycles, configuring refresh control circuits to use redundant word-lines in generating additional refresh cycles for redundant rows of memory cells, and combinations thereof. In one aspect, word-line fuses indicate modes of use as: unused, replacement, additional refresh, and replacement with additional refresh. The refresh control circuit utilizes these modes in combination with the X-address stored in the word-line fuses for controlling the generation of additional refresh cycles toward overcoming insufficient data retention intervals in select memory cell rows.
    • 描述了用于减少泄漏和提高修复产量的动态随机存取存储器(DRAM)电路和方法。 根据本发明,通过在功率控制的单个激活中分组刷新周期,使用限制电路或熔丝来减轻与位线和字线的微桥接相关联的功率损耗,调制位线 在预充电周期结束时配置刷新控制电路以使用冗余字线来产生冗余的存储器单元行的附加刷新周期,以及它们的组合。 在一个方面,字线保险丝将使用模式指示为:未使用,替换,附加刷新以及附加刷新的替换。 刷新控制电路利用这些模式与存储在字线保险丝中的X地址相组合,用于控制产生额外的刷新周期以克服选择存储单元行中的不充足的数据保留间隔。