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1. 发明授权

US5751618A Arithmetic circuit 失效
标题翻译：算术电路
公开(公告)号：US5751618A
公开(公告)日：1998-05-12
申请号：US391871
申请日：1995-02-22
申请人： Shigeshi Abiko , Shintaro Mizushima , Marc Couvrat
发明人： Shigeshi Abiko , Shintaro Mizushima , Marc Couvrat
IPC分类号： G06F7/50 , G06F7/506 , G06F7/507 , G06F7/53 , G06F7/533 , G06F7/57 , G06F17/10 , G06F7/38
CPC分类号： G06F7/57
摘要： An arithmetic circuit is provided in which the circuit scale can be reduced and the circuit delay can be shortened. The upper 24 bits and lower 16 bits of the 40 bit data A and B, that is input into the arithmetic circuit 100, are calculated in the first arithmetic circuit 110 and the second arithmetic circuit 120, respectively. The carry transmission control circuit 130 transmits the carry between the arithmetic circuit 120 and the arithmetic circuit 110 when the arithmetic circuit dividing signal p does not divide the arithmetic circuit, and the command control circuit 140 outputs an identical command to each of the arithmetic circuits. As a result, this circuit becomes an arithmetic circuit of 40 bits. The carry transmission control circuit 130 stops the transmission of the carry between the arithmetic circuit 120 and the arithmetic circuit 110 when the signal p divides the arithmetic circuit, and the command control circuit 140 outputs each of the independent commands to each of the arithmetic circuits. As a result, this circuit becomes a parallel arithmetic circuit of 24 bits and 16 bits.
摘要翻译：提供了一种算术电路，其中可以减小电路规模，并且可以缩短电路延迟。分别在第一运算电路110和第二运算电路120中计算输入到运算电路100的40位数据A和B的高24位和低16位。当运算电路分配信号p不分配算术电路时，进位传送控制电路130传送运算电路120和运算电路110之间的进位，并且命令控制电路140向每个运算电路输出相同的命令。结果，该电路成为40位的运算电路。当信号p分割运算电路时，进位传输控制电路130停止运算电路120和运算电路110之间的进位的传输，并且命令控制电路140将每个独立命令输出到每个运算电路。结果，该电路成为24位和16位的并行运算电路。

2. 发明授权

US06704582B2 Personalized incoming call signal for communication devices 有权
标题翻译：用于通信设备的个性化呼入信号
公开(公告)号：US06704582B2
公开(公告)日：2004-03-09
申请号：US09734299
申请日：2000-12-11
申请人： Laurent Le-Faucheur , Marc Couvrat
发明人： Laurent Le-Faucheur , Marc Couvrat
IPC分类号： H04M100
CPC分类号： H04M19/041
摘要： Apparatus and methods are presented to allow the creation of a personalized audio signal for a communication device., An option to record audio input and create a call signal audio file is selected via an input mechanism (203). Audio input is recorded when a record button (204) is pressed and the recording is terminated when the record button (204) is pressed a second time. Processing circuitry (220) optionally applies audio compression, filtering and encoding algorithms to said audio input and creates a call signal audio file. The call signal audio file is then stored in the memory circuitry designated for call signal audio files (210). Additional audio output circuitry (207) plays the call signal audio file when an incoming call is detected by the transceiver (201).
摘要翻译：呈现装置和方法以允许为通信设备创建个性化音频信号。经由输入机构（203）选择记录音频输入和创建呼叫信号音频文件的选项。当按下记录按钮（204）时，记录音频输入，并且当第二次按下记录按钮（204）时终止记录。处理电路（220）可任选地将音频压缩，滤波和编码算法应用于所述音频输入并创建呼叫信号音频文件。然后，呼叫信号音频文件被存储在为呼叫信号音频文件（210）指定的存储器电路中。当收发机（201）检测到来话呼叫时，附加音频输出电路（207）播放呼叫信号音频文件。

3. 发明授权

US5483554A Modulator especially for digital cellular telephone system 失效
标题翻译：调制器特别适用于数字蜂窝电话系统
公开(公告)号：US5483554A
公开(公告)日：1996-01-09
申请号：US973905
申请日：1992-11-10
申请人： Gerard Chauvel , Gael Clave , Marc Couvrat
发明人： Gerard Chauvel , Gael Clave , Marc Couvrat
IPC分类号： H04B1/40 , H04B7/26 , H04L27/12 , H04L27/20 , H03C3/00 , H03K7/06
CPC分类号： H04L27/2017
摘要： Modulator especially for digital cellular telephone systems, characterised in that it comprises a programmable peripheral processor (25) carrying out, with the same circuits, the modulation function and the channel coder/decoder tasks.
摘要翻译：特别是用于数字蜂窝电话系统的调制器，其特征在于，它包括一个可编程的外围处理器（25），其具有相同的电路调制功能和信道编码器/解码器任务。

4. 发明授权

US06658578B1 Microprocessors 有权
标题翻译：微处理器
公开(公告)号：US06658578B1
公开(公告)日：2003-12-02
申请号：US09410977
申请日：1999-10-01
申请人： Gilbert Laurenti , Jean-Pierre Giacalone , Emmanuel Ego , Anne Lombardot , Francois Theodorou , Gael Clave , Yves Masse , Karim Djafarian , Armelle Laine , Jean-Louis Tardieux , Eric Ponsot , Herve Catan , Vincent Gillet , Mark Buser , Jean-Marc Bachot , Eric Badi , N. M. Ganesh , Walter A. Jackson , Jack Rosenzweig , Shigeshi Abiko , Douglas E. Deao , Frederic Nidegger , Marc Couvrat , Alain Boyadjian , Laurent Ichard , David Russell
发明人： Gilbert Laurenti , Jean-Pierre Giacalone , Emmanuel Ego , Anne Lombardot , Francois Theodorou , Gael Clave , Yves Masse , Karim Djafarian , Armelle Laine , Jean-Louis Tardieux , Eric Ponsot , Herve Catan , Vincent Gillet , Mark Buser , Jean-Marc Bachot , Eric Badi , N. M. Ganesh , Walter A. Jackson , Jack Rosenzweig , Shigeshi Abiko , Douglas E. Deao , Frederic Nidegger , Marc Couvrat , Alain Boyadjian , Laurent Ichard , David Russell
IPC分类号： G06F132
CPC分类号： G06F7/764 , G06F5/01 , G06F7/607 , G06F7/74 , G06F7/762 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30043 , G06F9/30083 , G06F9/3013 , G06F9/30149 , G06F9/30181 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/325 , G06F9/3552 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3867 , G06F9/3879 , G06F9/3885 , G06F9/3891 , G06K13/0825
摘要： A processor (100) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit (106), a program flow control unit (108), an address/data flow unit (110), a data computation unit (112), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit (104) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.
摘要翻译：提供了具有可变指令长度的可编程固定点数字信号处理器（DSP）的处理器（100），提供高代码密度和易于编程。架构和指令集针对低功耗和高效率执行DSP算法进行了优化，如无线电话以及纯控制任务。处理器包括指令缓冲器单元（106），程序流控制单元（108），地址/数据流单元（110），数据计算单元（112）和多个互连总线。双乘法累加块提高了处理性能。存储器接口单元（104）提供对数据和指令存储器的并行访问。指令缓冲器可用于在执行它之前缓冲单个和复合指令。解码机构被配置为对来自指令缓冲器的指令进行解码。使用复合指令可以有效地利用处理器内可用的带宽。可以从单独的第一和第二编程存储器指令编译软双存储器指令。可以有条件地执行或重复执行指令。位场处理和各种寻址模式，如循环缓冲区寻址，进一步支持DSP算法的执行。处理器包括具有管道保护功能的多级执行管线。各种功能模块可以单独断电以节省电力。处理器包括仿真和代码调试功能，支持缓存分析。

5. 发明授权

US06760837B1 Bit field processor 有权
标题翻译：位域处理器
公开(公告)号：US06760837B1
公开(公告)日：2004-07-06
申请号：US09410864
申请日：1999-10-01
申请人： Gilbert Laurenti , Jean-Pierre Giacalone , Emmanuel Ego , Marc Couvrat
发明人： Gilbert Laurenti , Jean-Pierre Giacalone , Emmanuel Ego , Marc Couvrat
IPC分类号： G06F700
CPC分类号： G06F7/764 , G06F5/01 , G06F5/10 , G06F7/607 , G06F7/74 , G06F7/762 , G06F9/30018 , G06F9/30101 , G06F9/3013 , G06F9/30134 , G06F9/3552 , G06F9/3891
摘要： An execution unit for a processing engine comprising first head part circuitry for deriving an intermediate signal from an input signal. The execution unit also comprises further circuitry which receives the intermediate signal and operates on it to produce a final signal. The further circuitry is typically configured to perform one or more signal processing functions in combination with the first circuitry, and generally comprises separate circuitry for each function. The intermediate signal is configured to be usable by each of the separate circuitry.
摘要翻译：一种用于处理引擎的执行单元，包括用于从输入信号导出中间信号的第一头部电路。执行单元还包括另外的电路，其接收中间信号并对其进行操作以产生最终信号。另外的电路通常被配置为与第一电路一起执行一个或多个信号处理功能，并且通常包括用于每个功能的单独的电路。中间信号被配置为可由每个分离电路使用。

6. 发明授权

US06438720B1 Host port interface 失效
标题翻译：主机端口接口
公开(公告)号：US06438720B1
公开(公告)日：2002-08-20
申请号：US08488394
申请日：1995-06-07
申请人： Frederic Boutaud , Jason Jones , Marc Couvrat , Oliver Mougenot , Mansoor A. Chishtie
发明人： Frederic Boutaud , Jason Jones , Marc Couvrat , Oliver Mougenot , Mansoor A. Chishtie
IPC分类号： G01R3128
CPC分类号： G06F11/24
摘要： A circuit for interfacing a processor with a host processor is provided that has a memory associated with the processor that is selectively accessible by either both the processors or by the host processor, a plurality of storage devices selectively interconnectable with the memory and host processor, and a logic circuit interconnected with the storage devices and processors for interconnecting at least a portion of the storage devices to the memory in response to signals from the processors. An integrated circuit is provided that has a microprocessor, a memory associated with said processor that is selectively accessible by said microprocessor or a host processor, a plurality of storage devices selectively interconnectable with said memory and said host processor, and a logic circuit interconnected with said storage devices and interconnectable with said processors for interconnecting at least a portion of said storage devices to said memory in response to signals from said processors.
摘要翻译：提供了一种用于将处理器与主机处理器进行接口的电路，其具有与处理器相关联的存储器，所述存储器可由处理器或主机处理器可选择地访问，可选择地与存储器和主机处理器互连的多个存储设备，以及与存储设备和处理器互连的逻辑电路，用于响应于来自处理器的信号将存储设备的至少一部分互连到存储器。提供了一种集成电路，其具有微处理器，与所述处理器相关联的存储器，所述存储器可由所述微处理器或主机处理器选择性地访问，可选择地与所述存储器和所述主处理器相互连接的多个存储设备，以及与所述主处理器互连的逻辑电路存储设备并且可与所述处理器互连，用于响应于来自所述处理器的信号将所述存储设备的至少一部分互连到所述存储器。

7. 发明授权

US5838934A Host port interface 失效
公开(公告)号：US5838934A
公开(公告)日：1998-11-17
申请号：US471900
申请日：1995-06-07
申请人： Frederic Boutaud , Jason Jones , Marc Couvrat , Oliver Mougenot , Mansoor A. Chishtie
发明人： Frederic Boutaud , Jason Jones , Marc Couvrat , Oliver Mougenot , Mansoor A. Chishtie
IPC分类号： G06F13/28 , G06F13/38 , G06F13/00
CPC分类号： G06F13/28 , G06F13/385
摘要： A circuit for interfacing a processor with a host processor is provided that has a memory associated with the processor that is selectively accessible by either both the processors or by the host processor, a plurality of storage devices selectively interconnectable with the memory and host processor, and a logic circuit interconnected with the storage devices and processors for interconnecting at least a portion of the storage devices to the memory in response to signals from the processors. An integrated circuit is provided that has a microprocessor, a memory associated with said processor that is selectively accessible by said microprocessor or a host processor, a plurality of storage devices selectively interconnectable with said memory and said host processor, and a logic circuit interconnected with said storage devices and interconnectable with said processors for interconnecting at least a portion of said storage devices to said memory in response to signals from said processors.

8. 发明授权

US5734927A System having registers for receiving data, registers for transmitting data, both at a different clock rate, and control circuitry for shifting the different clock rates 失效
标题翻译：具有用于接收数据的寄存器，用于以不同时钟速率发送数据的寄存器的系统以及用于移位不同时钟速率的控制电路
公开(公告)号：US5734927A
公开(公告)日：1998-03-31
申请号：US489463
申请日：1995-06-08
申请人： Frederic Boutaud , Marc Couvrat , Yves Masse , Mansoor A. Chishtie , Alain Vallauri , Ajay Padgaonkar , Jason Jones
发明人： Frederic Boutaud , Marc Couvrat , Yves Masse , Mansoor A. Chishtie , Alain Vallauri , Ajay Padgaonkar , Jason Jones
IPC分类号： G06F13/16 , G06F13/00
CPC分类号： G06F13/1673
摘要： An electronic device for transferring data between a serial port and a memory of a CPU is provided having a plurality of data registers for transferring data between said serial port and said memory in response to a first set of control signals, a data bus connected to said registers and said memory for passing data to and from said memory in response to a portion of said first set of control signals, first control circuitry for generating said first set of control signals and for generating at least one interrupt to said CPU, at least one control register connected to said first control circuitry for providing mode control information to said first control circuitry, a plurality of address registers for storing data address, at least one address generator connected to said address registers for automatically generating addresses in response to a second set of control signals, an address bus connected to said address registers, and second control circuitry connected to said address generator, a portion of said control register and said first control circuitry for generating said second set of control signals.
摘要翻译：提供一种用于在CPU的串行端口和存储器之间传送数据的电子设备，其具有多个数据寄存器，用于响应于第一组控制信号在所述串行端口和所述存储器之间传送数据，连接到所述串行端口的数据总线寄存器和用于响应于所述第一组控制信号的一部分将数据传送到所述存储器的所述存储器，用于产生所述第一组控制信号并用于向所述CPU产生至少一个中断的第一控制电路，至少一个连接到所述第一控制电路的控制寄存器，用于向所述第一控制电路提供模式控制信息，多个用于存储数据地址的地址寄存器，连接到所述地址寄存器的至少一个地址发生器，用于响应于第二组控制信号，连接到所述地址寄存器的地址总线，以及连接到所述地址字的第二控制电路所述控制寄存器的一部分和所述第一控制电路用于产生所述第二组控制信号。

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