专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06658578B1 Microprocessors 有权
标题翻译：微处理器
公开(公告)号：US06658578B1
公开(公告)日：2003-12-02
申请号：US09410977
申请日：1999-10-01
申请人： Gilbert Laurenti , Jean-Pierre Giacalone , Emmanuel Ego , Anne Lombardot , Francois Theodorou , Gael Clave , Yves Masse , Karim Djafarian , Armelle Laine , Jean-Louis Tardieux , Eric Ponsot , Herve Catan , Vincent Gillet , Mark Buser , Jean-Marc Bachot , Eric Badi , N. M. Ganesh , Walter A. Jackson , Jack Rosenzweig , Shigeshi Abiko , Douglas E. Deao , Frederic Nidegger , Marc Couvrat , Alain Boyadjian , Laurent Ichard , David Russell
发明人： Gilbert Laurenti , Jean-Pierre Giacalone , Emmanuel Ego , Anne Lombardot , Francois Theodorou , Gael Clave , Yves Masse , Karim Djafarian , Armelle Laine , Jean-Louis Tardieux , Eric Ponsot , Herve Catan , Vincent Gillet , Mark Buser , Jean-Marc Bachot , Eric Badi , N. M. Ganesh , Walter A. Jackson , Jack Rosenzweig , Shigeshi Abiko , Douglas E. Deao , Frederic Nidegger , Marc Couvrat , Alain Boyadjian , Laurent Ichard , David Russell
IPC分类号： G06F132
CPC分类号： G06F7/764 , G06F5/01 , G06F7/607 , G06F7/74 , G06F7/762 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30043 , G06F9/30083 , G06F9/3013 , G06F9/30149 , G06F9/30181 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/325 , G06F9/3552 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3867 , G06F9/3879 , G06F9/3885 , G06F9/3891 , G06K13/0825
摘要： A processor (100) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit (106), a program flow control unit (108), an address/data flow unit (110), a data computation unit (112), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit (104) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.
摘要翻译：提供了具有可变指令长度的可编程固定点数字信号处理器（DSP）的处理器（100），提供高代码密度和易于编程。架构和指令集针对低功耗和高效率执行DSP算法进行了优化，如无线电话以及纯控制任务。处理器包括指令缓冲器单元（106），程序流控制单元（108），地址/数据流单元（110），数据计算单元（112）和多个互连总线。双乘法累加块提高了处理性能。存储器接口单元（104）提供对数据和指令存储器的并行访问。指令缓冲器可用于在执行它之前缓冲单个和复合指令。解码机构被配置为对来自指令缓冲器的指令进行解码。使用复合指令可以有效地利用处理器内可用的带宽。可以从单独的第一和第二编程存储器指令编译软双存储器指令。可以有条件地执行或重复执行指令。位场处理和各种寻址模式，如循环缓冲区寻址，进一步支持DSP算法的执行。处理器包括具有管道保护功能的多级执行管线。各种功能模块可以单独断电以节省电力。处理器包括仿真和代码调试功能，支持缓存分析。

2. 发明授权

US06557097B1 Linear vector computation 有权
标题翻译：线性向量计算
公开(公告)号：US06557097B1
公开(公告)日：2003-04-29
申请号：US09411473
申请日：1999-10-01
申请人： Gael Clave , Karim Djafarian , Gilbert Laurenti
发明人： Gael Clave , Karim Djafarian , Gilbert Laurenti
IPC分类号： G06F1716
CPC分类号： G06F5/01 , G06F7/607 , G06F7/74 , G06F7/762 , G06F7/764 , G06F9/3001 , G06F9/30018 , G06F9/30032 , G06F9/30072 , G06F9/3012 , G06F9/30145 , G06F9/30149 , G06F9/32 , G06F9/321 , G06F9/325 , G06F9/3552 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3867 , G06F9/3879 , G06F9/3885 , G06F9/3891 , G06F17/16
摘要： A processing engine 10 provides computation of an output vector as a linear combination of N input vectors with N coefficients in an efficient manner. The processing engine includes a coefficient register 940 for holding a representation of each of N coefficients of a first input vector. A test unit 950 is provided for testing selected parts (e.g. bits) of the coefficient register for respective coefficient representations. An arithmetic unit 970 computes respective coordinates of an output vector by selective addition/subtraction of coordinates of a second input vector dependent on results of the coefficient representation tests. Power consumption can be kept low due to the use of a coefficient test operation in parallel with an ALU operation. Each coordinate of an output vector {right arrow over (Y)} can be computed with a N+1 step algorithm, the computation being done with bit test unit operating in parallel with an ALU according to the following equation: ∀ 1 ≤ j ≤ M ⁢ ⁢ Y j = ∑ 1 ≤ i ≤ N ⁢ ⁢ ( ( - 1 ) C i * X ij ) . At a step (i+1)1≦i≦N of the computation, a bit Ci+1 of the CPU register is addressed, this bit is tested in a temporary register and a conditional addition/subtraction of a coordinate of the second input vector Xij is performed.
摘要翻译：处理引擎10以有效的方式提供输出向量作为具有N个系数的N个输入向量的线性组合的计算。处理引擎包括用于保持第一输入向量的N个系数中的每一个的表示的系数寄存器940。提供测试单元950用于测试用于各个系数表示的系数寄存器的选定部分（例如位）。算术单元970根据系数表示测试的结果，通过选择性地相加/减去第二输入向量的坐标来计算输出向量的各个坐标。由于与ALU操作并行地使用系数测试操作，所以能够将功耗保持为低。输出向量的每个坐标{向右箭头（Y可以用N + 1步算法计算，根据以下等式，使用与ALU并行操作的位测试单元进行计算）：在步骤（i + 1 ）1 <= i <= N，CPU寄存器的位Ci + 1被寻址，该位在临时寄存器中被测试，并且执行第二输入向量Xij的坐标的条件相加/减法。

3. 发明授权

US5483554A Modulator especially for digital cellular telephone system 失效
标题翻译：调制器特别适用于数字蜂窝电话系统
公开(公告)号：US5483554A
公开(公告)日：1996-01-09
申请号：US973905
申请日：1992-11-10
申请人： Gerard Chauvel , Gael Clave , Marc Couvrat
发明人： Gerard Chauvel , Gael Clave , Marc Couvrat
IPC分类号： H04B1/40 , H04B7/26 , H04L27/12 , H04L27/20 , H03C3/00 , H03K7/06
CPC分类号： H04L27/2017
摘要： Modulator especially for digital cellular telephone systems, characterised in that it comprises a programmable peripheral processor (25) carrying out, with the same circuits, the modulation function and the channel coder/decoder tasks.
摘要翻译：特别是用于数字蜂窝电话系统的调制器，其特征在于，它包括一个可编程的外围处理器（25），其具有相同的电路调制功能和信道编码器/解码器任务。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式