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1. 发明申请

US20140089370A1 PARALLEL BIT REVERSAL DEVICES AND METHODS 有权
标题翻译：并行转换器件和方法
公开(公告)号：US20140089370A1
公开(公告)日：2014-03-27
申请号：US14118452
申请日：2011-12-31
申请人： Shaolin Xie , Donglin Wang , Jie Hao , Tao Wang , Leizu Yin
发明人： Shaolin Xie , Donglin Wang , Jie Hao , Tao Wang , Leizu Yin
IPC分类号： G06F17/14
CPC分类号： G06F17/142 , G06F7/762 , G06F7/768
摘要： A parallel bit reversal device and method. The device includes a parallel bit reversal unit, a butterfly computation and control unit, and a memory. The butterfly computation and control unit is coupled to the memory via a data bus. The parallel bit reversal unit is configured to bit-reverse butterfly group data used by the butterfly computation and control unit. The parallel bit reversal unit includes an address reversing logic coupled to the butterfly computation and control unit, and configured to perform mirror reversal and right-shift operations on a read address from the butterfly computation and control unit.
摘要翻译：一种并行位反转器件及方法。该装置包括并行位反转单元，蝶形计算和控制单元以及存储器。蝴蝶计算和控制单元通过数据总线耦合到存储器。并行位反转单元被配置为对蝶形计算和控制单元使用的蝶形组数据进行位反转。并行比特反转单元包括耦合到蝶形计算和控制单元的地址反转逻辑，并且被配置为对来自蝶形计算和控制单元的读取地址执行镜像反转和右移操作。

2. 发明授权

US07689635B2 Area efficient shift / rotate system 有权
标题翻译：区域高效换档/旋转系统
公开(公告)号：US07689635B2
公开(公告)日：2010-03-30
申请号：US11260863
申请日：2005-10-27
申请人： Shalini Gupta , Sumanta Sarkar
发明人： Shalini Gupta , Sumanta Sarkar
IPC分类号： G06F7/00
CPC分类号： G06F5/015 , G06F7/762 , G06F7/768
摘要： An area efficient data shifter/rotator using a barrel shifter. The invention is a circuit, which uses a single barrel shifter and is controllable to implement either a left or right shift or rotation of bits of a digital data word. The circuit is dynamically controllable to implement left or right shift of bits of the digital data word (both logical and arithmetic) and rotation (to the left or right) of bits of the word. The proposed circuit produces the required output in a single cycle.
摘要翻译：一种使用桶形移位器的区域高效数据移位器/旋转器。本发明是一种电路，其使用单个桶形移位器并且可控制地实现数字数据字的位的左移或右移或旋转。该电路是可动态控制的，以实现数字数据字（逻辑和运算）和字的位（左或右）的位的左移或右移。所提出的电路在单个周期中产生所需的输出。

3. 发明授权

US07620764B2 System, apparatus and method for data path routing configurable to perform dynamic bit permutations 有权
标题翻译：用于数据路径路由的系统，装置和方法可配置为执行动态位排列
公开(公告)号：US07620764B2
公开(公告)日：2009-11-17
申请号：US11768113
申请日：2007-06-25
申请人： Charle′ R. Rupp
发明人： Charle′ R. Rupp
IPC分类号： G06F13/00 , G06F9/00
CPC分类号： G06F7/762 , G06F5/015 , G06F7/768 , G06F13/4022
摘要： A system, apparatus and a method for routing data over fewer switches and interconnections among reconfigurable logic elements, and for adapting routing resources to dynamically perform complex bit-level permutations, such as shifting and bit reversal operations. In one embodiment, an exemplary silo routing circuit is formed upon a semiconductor substrate and routes data among a number of reconfigurable computational elements. The silo routing circuit comprises a plurality of input terminals and a plurality of output terminals. Further, the silo routing circuit includes a multi-stage interconnection network (“MIN”) of switches configurable to form data paths from any input terminal to any output terminal.
摘要翻译：一种用于在可重配置逻辑元件之间通过较少的交换机和互连路由数据的系统，装置和方法，并且用于调整路由资源以动态地执行诸如移位和位反转操作之类的复杂位级排列。在一个实施例中，示例性筒仓路由电路形成在半导体衬底上并在多个可重新配置的计算元件之间路由数据。筒仓路由电路包括多个输入端子和多个输出端子。此外，筒仓路由电路包括可配置为形成从任何输入端到任何输出端的数据路径的开关的多级互连网络（“MIN”）。

4. 发明申请

US20090177870A1 Method and System for a Wiring-Efficient Permute Unit 失效
标题翻译：一种有效的宽带单元的方法和系统
公开(公告)号：US20090177870A1
公开(公告)日：2009-07-09
申请号：US11968692
申请日：2008-01-03
申请人： Bruce M. Fleischer , Hung C. Ngo , Jun Sawada
发明人： Bruce M. Fleischer , Hung C. Ngo , Jun Sawada
IPC分类号： G06F9/305 , G06F13/00
CPC分类号： G06F9/30032 , G06F7/762 , G06F7/766 , G06F9/30036 , G06F9/3824 , G06F9/3826
摘要： A method of providing wiring efficiency in a permute unit. Multiple selectors receive input data and shared control signals from multiple register files. The permute unit includes multiple multiplexors (MUXs) coupled to multiple logical AND gates. The multiple logical AND gates are coupled to multiple logical OR gates. The logical AND gates are physically separated from the logical OR gates. The logical AND gates receive input from one or more output data signals from the selectors. The logical OR gates combine the one or more output signals from the logical AND gates and provide output data from the permute unit.
摘要翻译：一种在置换单元中提供布线效率的方法。多个选择器从多个寄存器文件接收输入数据和共享控制信号。置换单元包括耦合到多个逻辑与门的多个多路复用器（MUX）。多个逻辑与门被耦合到多个逻辑或门。逻辑“与”门与逻辑或门物理分离。逻辑与门接收来自选择器的一个或多个输出数据信号的输入。逻辑或门组合来自逻辑与门的一个或多个输出信号，并提供来自置换单元的输出数据。

5. 发明申请

US20070250656A1 SYSTEM, APPARATUS AND METHOD FOR DATA PATH ROUTING CONFIGURABLE TO PERFORM DYNAMIC BIT PERMUTATIONS 有权
标题翻译：用于数据路径路由的系统，装置和方法可配置为执行动态位传输
公开(公告)号：US20070250656A1
公开(公告)日：2007-10-25
申请号：US11768113
申请日：2007-06-25
申请人： Charle' RUPP
发明人： Charle' RUPP
IPC分类号： G06F13/00
CPC分类号： G06F7/762 , G06F5/015 , G06F7/768 , G06F13/4022
摘要： A system, apparatus and a method for routing data over fewer switches and interconnections among reconfigurable logic elements, and for adapting routing resources to dynamically perform complex bit-level permutations, such as shifting and bit reversal operations. In one embodiment, an exemplary silo routing circuit is formed upon a semiconductor substrate and routes data among a number of reconfigurable computational elements. The silo routing circuit comprises a plurality of input terminals and a plurality of output terminals. Further, the silo routing circuit includes a multi-stage interconnection network (“MIN”) of switches configurable to form data paths from any input terminal to any output terminal.
摘要翻译：一种用于在可重配置逻辑元件之间通过较少的交换机和互连路由数据的系统，装置和方法，并且用于调整路由资源以动态地执行诸如移位和位反转操作之类的复杂位级排列。在一个实施例中，示例性筒仓路由电路形成在半导体衬底上并在多个可重新配置的计算元件之间路由数据。筒仓路由电路包括多个输入端子和多个输出端子。此外，筒仓路由电路包括可配置为形成从任何输入端到任何输出端的数据路径的开关的多级互连网络（“MIN”）。

6. 发明授权

US06990570B2 Processor with a computer repeat instruction 有权
标题翻译：具有计算机重复指令的处理器
公开(公告)号：US06990570B2
公开(公告)日：2006-01-24
申请号：US09410730
申请日：1999-10-01
申请人： Yves Masse , Gilbert Laurenti , Alain Boyadjian
发明人： Yves Masse , Gilbert Laurenti , Alain Boyadjian
IPC分类号： G06F15/00
CPC分类号： G06F7/764 , G06F5/01 , G06F7/607 , G06F7/74 , G06F7/762 , G06F9/30018 , G06F9/30032 , G06F9/3005 , G06F9/30065 , G06F9/30149 , G06F9/32 , G06F9/321 , G06F9/325 , G06F9/3552 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3867 , G06F9/3879 , G06F9/3885 , G06F9/3891
摘要： A processing engine, such as a digital signal processor, includes an execution mechanism, a repeat count register and a repeat count index register. The execution mechanism is operable for a repeat instruction to initialize the repeat count index register with the content of the repeat count register, and to modify the content of the repeat count register. The repeat instruction comprises two parts, the first of which initializes the repeat count index register and initiates repeat of a subsequent instruction, and the second part of which modifies the content of the repeat count register.
摘要翻译：诸如数字信号处理器的处理引擎包括执行机构，重复计数寄存器和重复计数指数寄存器。执行机制可操作用于重复指令，用重复计数寄存器的内容初始化重复计数指数寄存器，并修改重复计数寄存器的内容。重复指令包括两部分，第一部分初始化重复计数指数寄存器，并启动后续指令的重复，第二部分修改重复计数寄存器的内容。

7. 发明申请

US20050198473A1 Multiplexing operations in SIMD processing 审中-公开
标题翻译： SIMD处理中的复用操作
公开(公告)号：US20050198473A1
公开(公告)日：2005-09-08
申请号：US10889366
申请日：2004-07-13
申请人： Simon Ford
发明人： Simon Ford
IPC分类号： G06F9/38 , G06F7/76 , G06F9/305 , G06F9/34 , G06F15/80 , G06F9/00
CPC分类号： G06F7/762 , G06F7/76 , G06F7/768 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/30138 , G06F9/3016 , G06F9/30167 , G06F9/3822
摘要： A data processing apparatus, method and computer program product. The apparatus comprising: a register data store comprising at least three general purpose registers each operable to store a plurality of data elements; an instruction decoder operable to decode a multiplex instruction; a data processor operable to process said plurality of data elements in parallel, said data processor being controlled by said instruction decoder; and in response to said decoded multiplex instruction, said data processor being operable to specify: two of said at least three general-purpose registers as source registers, each operable to store a plurality of source data elements; a further one of said at least three registers as a control register operable to store a plurality of control values; and one of said control, or said two source registers as a destination register operable to store a plurality of resultant data elements; wherein in response to each of said plurality of control values said data processor is operable to select a corresponding data element from one of said two source registers, and to store said corresponding data element as a resultant data element in said destination register.
摘要翻译：数据处理装置，方法和计算机程序产品。该装置包括：寄存器数据存储器，包括至少三个通用寄存器，每个通用寄存器可操作以存储多个数据元素; 指令解码器，用于解码多路复用指令; 数据处理器，可操作以并行处理所述多个数据元素，所述数据处理器由所述指令解码器控制; 并且响应于所述解码的多路复用指令，所述数据处理器可操作以指定：所述至少三个通用寄存器中的两个作为源寄存器，每个可用于存储多个源数据元素; 所述至少三个寄存器中的另一个作为可操作以存储多个控制值的控制寄存器; 以及所述控制或所述两个源寄存器之一作为可操作以存储多个结果数据元素的目的地寄存器; 其中响应于所述多个控制值中的每一个，所述数据处理器可操作以从所述两个源寄存器之一中选择相应的数据元素，并将所述对应的数据元素作为结果数据元素存储在所述目的寄存器中。

8. 发明授权

US06901420B2 Method and apparatus for performing packed shift operations 失效
标题翻译：用于执行打包换档操作的方法和装置
公开(公告)号：US06901420B2
公开(公告)日：2005-05-31
申请号：US10623062
申请日：2003-07-18
申请人： Derrick Chu Lin , Punit Minocha , Alexander D. Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
发明人： Derrick Chu Lin , Punit Minocha , Alexander D. Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
IPC分类号： G06F7/00 , G06F5/01 , G06F7/499 , G06F7/76 , G06F9/30 , G06F9/315 , G06F9/38 , G11C16/04
CPC分类号： G06F7/762 , G06F5/01 , G06F7/49994 , G06F7/76 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/30167 , G06F9/3885
摘要： A method and apparatus for performing a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.
摘要翻译：一种用于对具有多个值的打包数据元素执行移位操作的方法和装置。所述装置具有多个多路复用器，所述多个多路复用器中的每一个具有第一输入，第二输入，选择输入和输出。表示在第一总线上的移位的打包中间结果的多个比特中的每一个被耦合到对应的第一输入。表示多个值之一的替换位的多个比特中的每一个被耦合到对应的第二输入。由校正电路驱动的多个比特中的每一个被耦合到对应的选择输入。每个输出对应于移位包装结果的一位。

9. 发明授权

US06760837B1 Bit field processor 有权
标题翻译：位域处理器
公开(公告)号：US06760837B1
公开(公告)日：2004-07-06
申请号：US09410864
申请日：1999-10-01
申请人： Gilbert Laurenti , Jean-Pierre Giacalone , Emmanuel Ego , Marc Couvrat
发明人： Gilbert Laurenti , Jean-Pierre Giacalone , Emmanuel Ego , Marc Couvrat
IPC分类号： G06F700
CPC分类号： G06F7/764 , G06F5/01 , G06F5/10 , G06F7/607 , G06F7/74 , G06F7/762 , G06F9/30018 , G06F9/30101 , G06F9/3013 , G06F9/30134 , G06F9/3552 , G06F9/3891
摘要： An execution unit for a processing engine comprising first head part circuitry for deriving an intermediate signal from an input signal. The execution unit also comprises further circuitry which receives the intermediate signal and operates on it to produce a final signal. The further circuitry is typically configured to perform one or more signal processing functions in combination with the first circuitry, and generally comprises separate circuitry for each function. The intermediate signal is configured to be usable by each of the separate circuitry.
摘要翻译：一种用于处理引擎的执行单元，包括用于从输入信号导出中间信号的第一头部电路。执行单元还包括另外的电路，其接收中间信号并对其进行操作以产生最终信号。另外的电路通常被配置为与第一电路一起执行一个或多个信号处理功能，并且通常包括用于每个功能的单独的电路。中间信号被配置为可由每个分离电路使用。

10. 发明授权

US06622242B1 System and method for performing generalized operations in connection with bits units of a data word 有权
标题翻译：用于执行与数据字的位单元相关的广义操作的系统和方法
公开(公告)号：US06622242B1
公开(公告)日：2003-09-16
申请号：US09545018
申请日：2000-04-07
申请人： Guy L. Steele, Jr.
发明人： Guy L. Steele, Jr.
IPC分类号： G06F700
CPC分类号： G06F9/30032 , G06F5/015 , G06F7/762 , G06F7/768 , G06F9/30018 , G06F9/30036
摘要： A functional unit is described for selectively performing a number of types of bit rearrangement operations, including a generalized bit reverse operation and a generalized shuffle/unshuffle operation, and in addition left and right unsigned shift operations and an arithmetic shift right operation. The functional unit includes a shifter array and a control signal generator. The shifter array includes a plurality of selector circuits arrayed in a number of stages for shifting bits of an input data word in accordance with control signals, the output of the last stage corresponding to a rearranged output data word. The control signal generator generates control signals in response to rearrangement operation type and pattern information.
摘要翻译：描述了功能单元，用于选择性地执行多种类型的比特重排操作，包括广义比特反向操作和广义混洗/混洗操作，以及左和右无符号移位操作和算术右移操作。功能单元包括移位器阵列和控制信号发生器。移位器阵列包括多个选择器电路，其以多个级数排列，用于根据控制信号移位输入数据字的位，最后级的输出对应于重新排列的输出数据字。控制信号发生器响应于重排操作类型和模式信息产生控制信号。

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