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1. 发明授权

US06658578B1 Microprocessors 有权
标题翻译：微处理器
公开(公告)号：US06658578B1
公开(公告)日：2003-12-02
申请号：US09410977
申请日：1999-10-01
申请人： Gilbert Laurenti , Jean-Pierre Giacalone , Emmanuel Ego , Anne Lombardot , Francois Theodorou , Gael Clave , Yves Masse , Karim Djafarian , Armelle Laine , Jean-Louis Tardieux , Eric Ponsot , Herve Catan , Vincent Gillet , Mark Buser , Jean-Marc Bachot , Eric Badi , N. M. Ganesh , Walter A. Jackson , Jack Rosenzweig , Shigeshi Abiko , Douglas E. Deao , Frederic Nidegger , Marc Couvrat , Alain Boyadjian , Laurent Ichard , David Russell
发明人： Gilbert Laurenti , Jean-Pierre Giacalone , Emmanuel Ego , Anne Lombardot , Francois Theodorou , Gael Clave , Yves Masse , Karim Djafarian , Armelle Laine , Jean-Louis Tardieux , Eric Ponsot , Herve Catan , Vincent Gillet , Mark Buser , Jean-Marc Bachot , Eric Badi , N. M. Ganesh , Walter A. Jackson , Jack Rosenzweig , Shigeshi Abiko , Douglas E. Deao , Frederic Nidegger , Marc Couvrat , Alain Boyadjian , Laurent Ichard , David Russell
IPC分类号： G06F132
CPC分类号： G06F7/764 , G06F5/01 , G06F7/607 , G06F7/74 , G06F7/762 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30043 , G06F9/30083 , G06F9/3013 , G06F9/30149 , G06F9/30181 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/325 , G06F9/3552 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3867 , G06F9/3879 , G06F9/3885 , G06F9/3891 , G06K13/0825
摘要： A processor (100) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit (106), a program flow control unit (108), an address/data flow unit (110), a data computation unit (112), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit (104) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.
摘要翻译：提供了具有可变指令长度的可编程固定点数字信号处理器（DSP）的处理器（100），提供高代码密度和易于编程。架构和指令集针对低功耗和高效率执行DSP算法进行了优化，如无线电话以及纯控制任务。处理器包括指令缓冲器单元（106），程序流控制单元（108），地址/数据流单元（110），数据计算单元（112）和多个互连总线。双乘法累加块提高了处理性能。存储器接口单元（104）提供对数据和指令存储器的并行访问。指令缓冲器可用于在执行它之前缓冲单个和复合指令。解码机构被配置为对来自指令缓冲器的指令进行解码。使用复合指令可以有效地利用处理器内可用的带宽。可以从单独的第一和第二编程存储器指令编译软双存储器指令。可以有条件地执行或重复执行指令。位场处理和各种寻址模式，如循环缓冲区寻址，进一步支持DSP算法的执行。处理器包括具有管道保护功能的多级执行管线。各种功能模块可以单独断电以节省电力。处理器包括仿真和代码调试功能，支持缓存分析。

2. 发明授权

US06760837B1 Bit field processor 有权
标题翻译：位域处理器
公开(公告)号：US06760837B1
公开(公告)日：2004-07-06
申请号：US09410864
申请日：1999-10-01
申请人： Gilbert Laurenti , Jean-Pierre Giacalone , Emmanuel Ego , Marc Couvrat
发明人： Gilbert Laurenti , Jean-Pierre Giacalone , Emmanuel Ego , Marc Couvrat
IPC分类号： G06F700
CPC分类号： G06F7/764 , G06F5/01 , G06F5/10 , G06F7/607 , G06F7/74 , G06F7/762 , G06F9/30018 , G06F9/30101 , G06F9/3013 , G06F9/30134 , G06F9/3552 , G06F9/3891
摘要： An execution unit for a processing engine comprising first head part circuitry for deriving an intermediate signal from an input signal. The execution unit also comprises further circuitry which receives the intermediate signal and operates on it to produce a final signal. The further circuitry is typically configured to perform one or more signal processing functions in combination with the first circuitry, and generally comprises separate circuitry for each function. The intermediate signal is configured to be usable by each of the separate circuitry.
摘要翻译：一种用于处理引擎的执行单元，包括用于从输入信号导出中间信号的第一头部电路。执行单元还包括另外的电路，其接收中间信号并对其进行操作以产生最终信号。另外的电路通常被配置为与第一电路一起执行一个或多个信号处理功能，并且通常包括用于每个功能的单独的电路。中间信号被配置为可由每个分离电路使用。

3. 发明申请

US20150350666A1 BLOCK-BASED STATIC REGION DETECTION FOR VIDEO PROCESSING 有权
标题翻译：用于视频处理的基于块的静态区域检测
公开(公告)号：US20150350666A1
公开(公告)日：2015-12-03
申请号：US14287967
申请日：2014-05-27
申请人： Vladimir Kovacevic , Zdravko Pantic , Aleksandar Beric , Ramanathan Sethuraman , Jean-Pierre Giacalone , Anton Igorevich Veselov , Marat Ravilevich Gilmutdinov
发明人： Vladimir Kovacevic , Zdravko Pantic , Aleksandar Beric , Ramanathan Sethuraman , Jean-Pierre Giacalone , Anton Igorevich Veselov , Marat Ravilevich Gilmutdinov
IPC分类号： H04N19/503
CPC分类号： H04N19/503 , H04N19/102 , H04N19/137 , H04N19/14 , H04N19/176 , H04N19/587 , H04N19/85
摘要： Methods, apparatus, systems and articles of manufacture to perform block-based static region detection for video processing are disclosed. Disclosed example video processing methods include segmenting pixels in a first frame of a video sequence into a first plurality of pixel blocks. Such example methods can also include processing the first plurality of pixel blocks and a second plurality of pixel blocks corresponding to a prior second frame of the video sequence to create, based on a first criterion, a map identifying one or more static pixel blocks in the first plurality of pixel blocks. Such example methods can further include identifying, based on the map, a static region in the first frame of the video sequence.
摘要翻译：公开了用于执行视频处理的基于块的静态区域检测的方法，装置，系统和制品。公开的示例视频处理方法包括将视频序列的第一帧中的像素分割为第一多个像素块。这样的示例性方法还可以包括处理第一多个像素块和与视频序列的先前第二帧相对应的第二多个像素块，以基于第一准则创建标识一个或多个静态像素块中的一个或多个静态像素块的映射第一多个像素块。这样的示例方法还可以包括基于该图来识别视频序列的第一帧中的静态区域。

4. 发明授权

US07394412B2 Unified interleaver/de-interleaver 有权
标题翻译：统一交织器/解交织器
公开(公告)号：US07394412B2
公开(公告)日：2008-07-01
申请号：US10758663
申请日：2004-01-15
申请人： Zhenguo Gu , Jean-Pierre Giacalone , Alexandra Raphaele Bireau
发明人： Zhenguo Gu , Jean-Pierre Giacalone , Alexandra Raphaele Bireau
IPC分类号： H03M7/00 , G06F12/00
CPC分类号： H03M13/6519 , H03M13/27 , H03M13/2714 , H03M13/2721 , H03M13/2764 , H03M13/2771
摘要： An interleaver/de-interleaver that may be used for multiple interleaving algorithms and look up tables (LUTs) of one or more interleaving standards. In at least some embodiments, the interleaver/de-interleaver may comprise an initial value selector, offset selector, and a pruning adjuster coupled to a combining block. The interleaver/de-interleaver may further comprise a boundary regulator coupled to the combining block, wherein the boundary regulator is configurable to modify an output of the combining block according to one or more pre-determined rules. The interleaver/de-interleaver may further comprise a controller coupled to, at least, the initial value selector, the offset value selector, and the offset adjuster, whereby the interleaver/de-interleaver may be used to interleave or de-interleave a block of data in accordance with a plurality of interleaving algorithms.
摘要翻译：可以用于一个或多个交织标准的多个交织算法和查询表（LUT）的交织器/解交织器。在至少一些实施例中，交织器/解交织器可以包括耦合到组合块的初始值选择器，偏移选择器和修剪调整器。交织器/解交织器还可以包括耦合到组合块的边界调节器，其中边界调节器可配置成根据一个或多个预定规则修改组合块的输出。交织器/解交织器还可以包括耦合到至少初始值选择器，偏移值选择器和偏移调整器的控制器，由此交织器/解交织器可以用于交织或解交织块的数据根据多个交织算法。

5. 发明申请

US20050157685A1 Unified interleaver/de-interleaver 有权
标题翻译：统一交织器/解交织器
公开(公告)号：US20050157685A1
公开(公告)日：2005-07-21
申请号：US10758663
申请日：2004-01-15
申请人： Zhenguo Gu , Jean-Pierre Giacalone , Alexandra Bireau
发明人： Zhenguo Gu , Jean-Pierre Giacalone , Alexandra Bireau
IPC分类号： H03M13/27 , H04B7/216
CPC分类号： H03M13/6519 , H03M13/27 , H03M13/2714 , H03M13/2721 , H03M13/2764 , H03M13/2771
摘要： An interleaver/de-interleaver that may be used for multiple interleaving algorithms and look up tables (LUTs) of one or more interleaving standards. In at least some embodiments, the interleaver/de-interleaver may comprise an initial value selector, offset selector, and a pruning adjuster coupled to a combining block. The interleaver/de-interleaver may further comprise a boundary regulator coupled to the combining block, wherein the boundary regulator is configurable to modify an output of the combining block according to one or more pre-determined rules. The interleaver/de-interleaver may further comprise a controller coupled to, at least, the initial value selector, the offset value selector, and the offset adjuster, whereby the interleaver/de-interleaver may be used to interleave or de-interleave a block of data in accordance with a plurality of interleaving algorithms.
摘要翻译：可以用于一个或多个交织标准的多个交织算法和查询表（LUT）的交织器/解交织器。在至少一些实施例中，交织器/解交织器可以包括耦合到组合块的初始值选择器，偏移选择器和修剪调整器。交织器/解交织器还可以包括耦合到组合块的边界调节器，其中边界调节器可配置成根据一个或多个预定规则修改组合块的输出。交织器/解交织器还可以包括耦合到至少初始值选择器，偏移值选择器和偏移调整器的控制器，由此交织器/解交织器可以用于交织或解交织块的数据根据多个交织算法。

6. 发明授权

US06571268B1 Multiplier accumulator circuits 有权
标题翻译：乘法器累加器电路
公开(公告)号：US06571268B1
公开(公告)日：2003-05-27
申请号：US09411167
申请日：1999-10-01
申请人： Jean-Pierre Giacalone , Francois Theodorou , Alain Boyadjian
发明人： Jean-Pierre Giacalone , Francois Theodorou , Alain Boyadjian
IPC分类号： G06F738
CPC分类号： G06F7/5338 , G06F5/01 , G06F7/49963 , G06F7/49968 , G06F7/5443 , G06F7/607 , G06F7/74 , G06F7/762 , G06F7/764 , G06F9/30018 , G06F9/30032 , G06F9/3005 , G06F9/3012 , G06F9/30149 , G06F9/32 , G06F9/321 , G06F9/3552 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3867 , G06F9/3879 , G06F9/3885 , G06F9/3891 , G06F2207/382
摘要： A multiply-accumulate (MAC) unit, having a first binary operand X, a second binary operand Y, a third binary operand, Booth recode logic for generating a plurality of partial products from said first and second operands, a Wallace tree adder for reducing the partial products and for selectively arithmetically combining the reduced partial products with said third operand, a final adder for generating a final sum, and a saturation circuitry for selectively rounding or saturating said final sum is provided. A dual MAC unit is also provided.
摘要翻译：具有第一二进制操作数X，第二二进制操作数Y，第三二进制操作数，用于从所述第一和第二操作数产生多个部分乘积的布斯重写逻辑的乘法累加（MAC）单元，用于减少提供了部分乘积和用于选择性地将减少的部分乘积与所述第三操作数组合，用于产生最终和的最终加法器和用于选择性地舍入或饱和所述最终和的饱和电路。还提供了双MAC单元。

7. 发明申请

US20090115597A1 ENERGY SAVING AND SECURITY SYSTEM 审中-公开
标题翻译：能源节约与安全体系
公开(公告)号：US20090115597A1
公开(公告)日：2009-05-07
申请号：US12255205
申请日：2008-10-21
申请人： Jean-Pierre Giacalone
发明人： Jean-Pierre Giacalone
IPC分类号： G08B29/00
CPC分类号： G05B15/02 , H04L12/2827
摘要： A system for administrating a network of heating, cooling, lighting, and motion sensors in a building and using the derived information for detecting status changes in the environmental factors being monitored for subsequent use.
摘要翻译：一种用于在建筑物中管理加热，制冷，照明和运动传感器网络的系统，并且使用导出的信息来检测所监视的环境因素的状态变化以供随后使用。

8. 发明授权

US07047272B2 Rounding mechanisms in processors 有权
标题翻译：处理器中的四舍五入机制
公开(公告)号：US07047272B2
公开(公告)日：2006-05-16
申请号：US09411186
申请日：1999-10-01
申请人： Jean-Pierre Giacalone , Anne Lombardot , Francois Theodorou
发明人： Jean-Pierre Giacalone , Anne Lombardot , Francois Theodorou
IPC分类号： G06F7/38 , G06F7/00
CPC分类号： G06F7/764 , G06F5/01 , G06F7/48 , G06F7/49952 , G06F7/49963 , G06F7/5443 , G06F7/607 , G06F7/74 , G06F7/762 , G06F9/30014 , G06F9/3891
摘要： An arithmetic unit, for example a multiply and accumulate (MAC) unit 42, for a processing engine includes a partial product reduction tree 480. The partial product reduction tree will generate carry results and provides a final output to a final adder 470 connected to the partial production reduction tree. Unbiased rounding logic 476 is provided. A carry propagation tree is responsive to the carry results for anticipating a zero on each of N least significant bits of the final adder. When zero is anticipated on each of N least significant bits of the final adder, the carry propagation tree is operable to generate an output signal 477 which is used by the unbiased rounding stage to force the (N+1)th least significant bit of the final adder to zero. Through the use of a carry propagation tree to predict, or anticipate zeros on the N least significant bits, unbiased rounding can be effected without a time penalty in that a carry propagation tree can be configured to be at least a rapid as the carry propagation of the final adder. Where a zero anticipation function is provided, this can also be mapped onto the carry propagation tree, thus providing an efficient hardware implementation through sharing of that hardware between functions.
摘要翻译：用于处理引擎的运算单元，例如乘法和累加（MAC）单元42包括部分乘积减少树480.部分乘积减少树将产生进位结果，并将最终输出提供给连接到部分减产树。提供无偏差的舍入逻辑476。进位传播树响应于进位结果，以预测最终加法器的N个最低有效位中的每一个上的零。当预期在最终加法器的N个最低有效位中的每一个零时，进位传播树可操作以产生输出信号477，该输出信号由无偏差舍入级用来强制第（N + 1）个最低有效位最终加法器为零。通过使用进位传播树来预测或预测N个最低有效位上的零，可以实现无偏差舍入，而不会造成时间损失，因为进位传播树可以被配置为至少一个快速的进位传播，最后的加法器。在提供零预期功能的情况下，这也可以被映射到进位传播树上，从而通过在功能之间共享该硬件来提供有效的硬件实现。

9. 发明授权

US06930689B1 Hardware extensions for image and video processing 有权
标题翻译：用于图像和视频处理的硬件扩展
公开(公告)号：US06930689B1
公开(公告)日：2005-08-16
申请号：US09748512
申请日：2000-12-26
申请人： Jean-Pierre Giacalone , Herve Daniel
发明人： Jean-Pierre Giacalone , Herve Daniel
IPC分类号： G06F15/16
CPC分类号： G06F17/175 , G06F17/147 , H04N19/42 , H04N19/61
摘要： A processing device (200) includes three hardware extensions: a motion estimation extension 202, a pixel interpolation extension 204 and a DCT/iDCT extension 206. The hardware extensions perform functions which would otherwise be highly processor intensive, resulting in high power consumption and/or low quality video/imaging processing. The processing device 200 could be used, for example, in a mobile videophone 150.
摘要翻译：处理设备（200）包括三个硬件扩展：运动估计扩展202，像素内插扩展204和DCT / iDCT扩展206。硬件扩展执行功能，否则这些功能将是高度处理器密集型，导致高功耗和/或低质量视频/成像处理。处理装置200可以用于例如移动可视电话150中。

10. 发明授权

US06487576B1 Zero anticipation method and apparatus 有权
标题翻译：零预期方法和装置
公开(公告)号：US06487576B1
公开(公告)日：2002-11-26
申请号：US09411466
申请日：1999-10-01
申请人： Jean-Pierre Giacalone , Herve Catan , Anne Lombardot
发明人： Jean-Pierre Giacalone , Herve Catan , Anne Lombardot
IPC分类号： G06F700
CPC分类号： G06F7/508 , G06F5/01 , G06F7/02 , G06F7/49905 , G06F7/607 , G06F7/74 , G06F7/762 , G06F7/764 , G06F9/30094 , G06F9/3013
摘要： A zero anticipation mechanism for an arithmetic unit 42 of a processing engine includes an array of cells 420, 430 interconnected to produce an ordered sequence of intermediate anticipation signals. The array of cells includes cells connected to receive intermediate result signals from the arithmetic unit, cells for forwarding an intermediate anticipation signal supplied thereto, and cells for generating a combination of first intermediate anticipation signals and second intermediate anticipation signals supplied thereto. The zero anticipation mechanism implements a zero look-ahead mechanism which can predict a zero result 479 prior to the arithmetic unit completing an arithmetic operation.
摘要翻译：用于处理引擎的运算单元42的零预期机制包括互连的单元阵列420,430，以产生中间预期信号的有序序列。单元阵列包括连接以从运算单元接收中间结果信号的单元，用于转发提供给其的中间预期信号的单元，以及用于产生提供给其的第一中间预期信号和第二中间预期信号的组合的单元。零预期机制实现零预先机制，其可以在算术单元完成算术运算之前预测零结果479。

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