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1. 发明授权

US06658578B1 Microprocessors 有权
标题翻译：微处理器
公开(公告)号：US06658578B1
公开(公告)日：2003-12-02
申请号：US09410977
申请日：1999-10-01
申请人： Gilbert Laurenti , Jean-Pierre Giacalone , Emmanuel Ego , Anne Lombardot , Francois Theodorou , Gael Clave , Yves Masse , Karim Djafarian , Armelle Laine , Jean-Louis Tardieux , Eric Ponsot , Herve Catan , Vincent Gillet , Mark Buser , Jean-Marc Bachot , Eric Badi , N. M. Ganesh , Walter A. Jackson , Jack Rosenzweig , Shigeshi Abiko , Douglas E. Deao , Frederic Nidegger , Marc Couvrat , Alain Boyadjian , Laurent Ichard , David Russell
发明人： Gilbert Laurenti , Jean-Pierre Giacalone , Emmanuel Ego , Anne Lombardot , Francois Theodorou , Gael Clave , Yves Masse , Karim Djafarian , Armelle Laine , Jean-Louis Tardieux , Eric Ponsot , Herve Catan , Vincent Gillet , Mark Buser , Jean-Marc Bachot , Eric Badi , N. M. Ganesh , Walter A. Jackson , Jack Rosenzweig , Shigeshi Abiko , Douglas E. Deao , Frederic Nidegger , Marc Couvrat , Alain Boyadjian , Laurent Ichard , David Russell
IPC分类号： G06F132
CPC分类号： G06F7/764 , G06F5/01 , G06F7/607 , G06F7/74 , G06F7/762 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30043 , G06F9/30083 , G06F9/3013 , G06F9/30149 , G06F9/30181 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/325 , G06F9/3552 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3867 , G06F9/3879 , G06F9/3885 , G06F9/3891 , G06K13/0825
摘要： A processor (100) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit (106), a program flow control unit (108), an address/data flow unit (110), a data computation unit (112), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit (104) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.
摘要翻译：提供了具有可变指令长度的可编程固定点数字信号处理器（DSP）的处理器（100），提供高代码密度和易于编程。架构和指令集针对低功耗和高效率执行DSP算法进行了优化，如无线电话以及纯控制任务。处理器包括指令缓冲器单元（106），程序流控制单元（108），地址/数据流单元（110），数据计算单元（112）和多个互连总线。双乘法累加块提高了处理性能。存储器接口单元（104）提供对数据和指令存储器的并行访问。指令缓冲器可用于在执行它之前缓冲单个和复合指令。解码机构被配置为对来自指令缓冲器的指令进行解码。使用复合指令可以有效地利用处理器内可用的带宽。可以从单独的第一和第二编程存储器指令编译软双存储器指令。可以有条件地执行或重复执行指令。位场处理和各种寻址模式，如循环缓冲区寻址，进一步支持DSP算法的执行。处理器包括具有管道保护功能的多级执行管线。各种功能模块可以单独断电以节省电力。处理器包括仿真和代码调试功能，支持缓存分析。

2. 发明授权

US06487576B1 Zero anticipation method and apparatus 有权
标题翻译：零预期方法和装置
公开(公告)号：US06487576B1
公开(公告)日：2002-11-26
申请号：US09411466
申请日：1999-10-01
申请人： Jean-Pierre Giacalone , Herve Catan , Anne Lombardot
发明人： Jean-Pierre Giacalone , Herve Catan , Anne Lombardot
IPC分类号： G06F700
CPC分类号： G06F7/508 , G06F5/01 , G06F7/02 , G06F7/49905 , G06F7/607 , G06F7/74 , G06F7/762 , G06F7/764 , G06F9/30094 , G06F9/3013
摘要： A zero anticipation mechanism for an arithmetic unit 42 of a processing engine includes an array of cells 420, 430 interconnected to produce an ordered sequence of intermediate anticipation signals. The array of cells includes cells connected to receive intermediate result signals from the arithmetic unit, cells for forwarding an intermediate anticipation signal supplied thereto, and cells for generating a combination of first intermediate anticipation signals and second intermediate anticipation signals supplied thereto. The zero anticipation mechanism implements a zero look-ahead mechanism which can predict a zero result 479 prior to the arithmetic unit completing an arithmetic operation.
摘要翻译：用于处理引擎的运算单元42的零预期机制包括互连的单元阵列420,430，以产生中间预期信号的有序序列。单元阵列包括连接以从运算单元接收中间结果信号的单元，用于转发提供给其的中间预期信号的单元，以及用于产生提供给其的第一中间预期信号和第二中间预期信号的组合的单元。零预期机制实现零预先机制，其可以在算术单元完成算术运算之前预测零结果479。

3. 发明授权

US07047272B2 Rounding mechanisms in processors 有权
标题翻译：处理器中的四舍五入机制
公开(公告)号：US07047272B2
公开(公告)日：2006-05-16
申请号：US09411186
申请日：1999-10-01
申请人： Jean-Pierre Giacalone , Anne Lombardot , Francois Theodorou
发明人： Jean-Pierre Giacalone , Anne Lombardot , Francois Theodorou
IPC分类号： G06F7/38 , G06F7/00
CPC分类号： G06F7/764 , G06F5/01 , G06F7/48 , G06F7/49952 , G06F7/49963 , G06F7/5443 , G06F7/607 , G06F7/74 , G06F7/762 , G06F9/30014 , G06F9/3891
摘要： An arithmetic unit, for example a multiply and accumulate (MAC) unit 42, for a processing engine includes a partial product reduction tree 480. The partial product reduction tree will generate carry results and provides a final output to a final adder 470 connected to the partial production reduction tree. Unbiased rounding logic 476 is provided. A carry propagation tree is responsive to the carry results for anticipating a zero on each of N least significant bits of the final adder. When zero is anticipated on each of N least significant bits of the final adder, the carry propagation tree is operable to generate an output signal 477 which is used by the unbiased rounding stage to force the (N+1)th least significant bit of the final adder to zero. Through the use of a carry propagation tree to predict, or anticipate zeros on the N least significant bits, unbiased rounding can be effected without a time penalty in that a carry propagation tree can be configured to be at least a rapid as the carry propagation of the final adder. Where a zero anticipation function is provided, this can also be mapped onto the carry propagation tree, thus providing an efficient hardware implementation through sharing of that hardware between functions.
摘要翻译：用于处理引擎的运算单元，例如乘法和累加（MAC）单元42包括部分乘积减少树480.部分乘积减少树将产生进位结果，并将最终输出提供给连接到部分减产树。提供无偏差的舍入逻辑476。进位传播树响应于进位结果，以预测最终加法器的N个最低有效位中的每一个上的零。当预期在最终加法器的N个最低有效位中的每一个零时，进位传播树可操作以产生输出信号477，该输出信号由无偏差舍入级用来强制第（N + 1）个最低有效位最终加法器为零。通过使用进位传播树来预测或预测N个最低有效位上的零，可以实现无偏差舍入，而不会造成时间损失，因为进位传播树可以被配置为至少一个快速的进位传播，最后的加法器。在提供零预期功能的情况下，这也可以被映射到进位传播树上，从而通过在功能之间共享该硬件来提供有效的硬件实现。

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