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1. 发明授权

US06658578B1 Microprocessors 有权
标题翻译：微处理器
公开(公告)号：US06658578B1
公开(公告)日：2003-12-02
申请号：US09410977
申请日：1999-10-01
申请人： Gilbert Laurenti , Jean-Pierre Giacalone , Emmanuel Ego , Anne Lombardot , Francois Theodorou , Gael Clave , Yves Masse , Karim Djafarian , Armelle Laine , Jean-Louis Tardieux , Eric Ponsot , Herve Catan , Vincent Gillet , Mark Buser , Jean-Marc Bachot , Eric Badi , N. M. Ganesh , Walter A. Jackson , Jack Rosenzweig , Shigeshi Abiko , Douglas E. Deao , Frederic Nidegger , Marc Couvrat , Alain Boyadjian , Laurent Ichard , David Russell
发明人： Gilbert Laurenti , Jean-Pierre Giacalone , Emmanuel Ego , Anne Lombardot , Francois Theodorou , Gael Clave , Yves Masse , Karim Djafarian , Armelle Laine , Jean-Louis Tardieux , Eric Ponsot , Herve Catan , Vincent Gillet , Mark Buser , Jean-Marc Bachot , Eric Badi , N. M. Ganesh , Walter A. Jackson , Jack Rosenzweig , Shigeshi Abiko , Douglas E. Deao , Frederic Nidegger , Marc Couvrat , Alain Boyadjian , Laurent Ichard , David Russell
IPC分类号： G06F132
CPC分类号： G06F7/764 , G06F5/01 , G06F7/607 , G06F7/74 , G06F7/762 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30043 , G06F9/30083 , G06F9/3013 , G06F9/30149 , G06F9/30181 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/325 , G06F9/3552 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3867 , G06F9/3879 , G06F9/3885 , G06F9/3891 , G06K13/0825
摘要： A processor (100) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit (106), a program flow control unit (108), an address/data flow unit (110), a data computation unit (112), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit (104) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.
摘要翻译：提供了具有可变指令长度的可编程固定点数字信号处理器（DSP）的处理器（100），提供高代码密度和易于编程。架构和指令集针对低功耗和高效率执行DSP算法进行了优化，如无线电话以及纯控制任务。处理器包括指令缓冲器单元（106），程序流控制单元（108），地址/数据流单元（110），数据计算单元（112）和多个互连总线。双乘法累加块提高了处理性能。存储器接口单元（104）提供对数据和指令存储器的并行访问。指令缓冲器可用于在执行它之前缓冲单个和复合指令。解码机构被配置为对来自指令缓冲器的指令进行解码。使用复合指令可以有效地利用处理器内可用的带宽。可以从单独的第一和第二编程存储器指令编译软双存储器指令。可以有条件地执行或重复执行指令。位场处理和各种寻址模式，如循环缓冲区寻址，进一步支持DSP算法的执行。处理器包括具有管道保护功能的多级执行管线。各种功能模块可以单独断电以节省电力。处理器包括仿真和代码调试功能，支持缓存分析。

2. 发明申请

US20110239196A1 Micro-Task Pipeline Visualization 审中-公开
标题翻译：微任务管道可视化
公开(公告)号：US20110239196A1
公开(公告)日：2011-09-29
申请号：US12757999
申请日：2010-04-10
申请人： Laurent Ichard
发明人： Laurent Ichard
IPC分类号： G06F11/36
CPC分类号： G06F11/3636 , G06F11/3648
摘要： A digital system is described that includes a plurality of interconnected functional modules each having one or more event signal outputs, wherein each module is configured to execute one or more tasks and to assert an event signal on its respective one or more event signal outputs to indicate progress of execution of a task. An event monitor is connected to receive from each of the plurality of functional modules the one or more event signal lines, wherein the event monitor is configured to record the occurrence of each event signal assertion. An interface module is coupled to the event monitor and has an output for transferring an indication of each event signal assertion to an external monitoring system.
摘要翻译：描述了一种数字系统，其包括多个互连的功能模块，每个功能模块具有一个或多个事件信号输出，其中每个模块被配置为执行一个或多个任务并且在其相应的一个或多个事件信号输出上断言事件信号以指示执行任务的进度。连接事件监视器以从多个功能模块中的每个功能模块接收一个或多个事件信号线，其中事件监视器被配置为记录每个事件信号断言的发生。接口模块耦合到事件监视器，并且具有用于将每个事件信号断言的指示传送到外部监视系统的输出。

3. 发明授权

US06795930B1 Microprocessor with selected partitions disabled during block repeat 有权
标题翻译：在块重复期间禁用选定分区的微处理器
公开(公告)号：US06795930B1
公开(公告)日：2004-09-21
申请号：US09716645
申请日：2000-11-20
申请人： Gilbert Laurenti , Olivier Morchipont , Laurent Ichard
发明人： Gilbert Laurenti , Olivier Morchipont , Laurent Ichard
IPC分类号： G06F126
CPC分类号： G06F9/3853 , G06F1/3203 , G06F1/3287 , G06F9/30036 , G06F9/30065 , G06F9/30145 , G06F9/30167 , G06F9/325 , G06F9/381 , Y02D10/171
摘要： A microprocessor and a method of operating the microprocessor are provided in which a portion of the microprocessor is partitioned into a plurality of partitions. A sequence of instructions is executed within an instruction pipeline of the microprocessor. A block of instructions within the sequence of instructions is repetitively executed in response to a local repeat instruction. Either prior to executing the block of instructions, or during the first iteration of the loop, a determination is made that at least one of the plurality of partitions is not needed to execute the block of instructions. Operation of the at least one identified partition is inhibited during the repetitive execution of the block of instructions in order to reduce power dissipation.
摘要翻译：提供微处理器和操作微处理器的方法，其中微处理器的一部分被分割成多个分区。在微处理器的指令流水线内执行指令序列。响应于本地重复指令重复地执行指令序列内的指令块。在执行指令块之前或在循环的第一次迭代期间，确定执行指令块不需要多个分区中的至少一个分区。在重复执行指令块期间，禁止至少一个识别的分区的操作，以便降低功耗。

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