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1. 发明授权

US07454169B2 Method and apparatus for use in securing an electronic device such as a cell phone 有权
标题翻译：用于固定诸如手机的电子设备的方法和装置
公开(公告)号：US07454169B2
公开(公告)日：2008-11-18
申请号：US10208965
申请日：2002-07-31
申请人： Joern Soerensen , Palle Birk , Frederic Boutaud
发明人： Joern Soerensen , Palle Birk , Frederic Boutaud
IPC分类号： H04B1/06
CPC分类号： G06F21/73 , H04W12/12 , H04W88/02
摘要： The present invention is directed to methods and apparatus which may be used to help prevent electronic devices, including cell phones, from operating with software copied from (and only authorized for use by or on) another device. A further aspect is a device, including a cell phone, for example, that employs any of such methods and apparatus. Aspects of the present invention compare a program identifier (associated with software stored in a device) to a reference identifier for the device, so as to determine whether the software is authorized for use with that device. Some embodiments respond to the comparison substantially in hardware, so that the software being checked is less able to prevent the device from being disabled in the event that the program identifier and the reference identifier do not match one another.
摘要翻译：本发明涉及可用于帮助防止电子设备（包括蜂窝电话）使用从另一设备复制（并且仅被授权使用或在其上）的软件操作的方法和装置。另一方面是一种设备，包括例如使用任何这样的方法和设备的蜂窝电话。本发明的方面将程序标识符（与存储在设备中的软件相关联）与设备的参考标识符进行比较，以便确定软件是否被授权与该设备一起使用。一些实施例基本上在硬件中对比较应答，使得被检查的软件在程序标识符和参考标识符彼此不匹配的情况下不太能够阻止该设备被禁用。

2. 发明申请

US20050251638A1 Devices, systems and methods for conditional instructions 审中-公开
标题翻译：用于条件指令的设备，系统和方法
公开(公告)号：US20050251638A1
公开(公告)日：2005-11-10
申请号：US11019875
申请日：2004-12-21
申请人： Frederic Boutaud , Peter Ehlig
发明人： Frederic Boutaud , Peter Ehlig
IPC分类号： G06F12/00
CPC分类号： G06F9/3013 , G06F9/30065 , G06F9/30101 , G06F9/30116 , G06F9/30123
摘要： A data processing device includes a circuit having status conditions wherein a particular set of the status conditions can occur in operation of the circuit. An instruction register operates to hold a branch instruction conditional on a particular set of the status conditions. A decoder is connected to the instruction register and the circuit. A program counter is coupled to the decoder wherein the decoder is operable to enter a branch address into the program counter in response to the branch instruction when the particular set of the status conditions of the circuit are present. Other data processing devices, systems and methods are also disclosed.
摘要翻译：数据处理装置包括具有状态条件的电路，其中可以在电路的操作中发生特定的状态条件集合。指令寄存器用于保持以特定状态条件为条件的分支指令。解码器连接到指令寄存器和电路。程序计数器耦合到解码器，其中当电路的状态条件的特定集合存在时，解码器可操作以响应于分支指令而将分支地址输入到程序计数器中。还公开了其他数据处理设备，系统和方法。

3. 发明授权

US06240505B1 System with wait state registers 失效
标题翻译：具有等待状态寄存器的系统
公开(公告)号：US06240505B1
公开(公告)日：2001-05-29
申请号：US09431506
申请日：1999-11-01
申请人： Frederic Boutaud , Peter N. Ehlig
发明人： Frederic Boutaud , Peter N. Ehlig
IPC分类号： G06F1500
CPC分类号： G01R31/318536 , G01R31/318505 , G06F9/30 , G06F9/30058 , G06F9/30072 , G06F9/30094 , G06F9/325 , G06F11/2733 , G06F11/3648 , G06F11/3652
摘要： A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.
摘要翻译：数据处理设备与具有接收者和不同通信响应周期的外围设备一起使用。数据处理装置包括数字处理器，其适于通过断言每个所选择的外围设备的地址来选择不同的外围设备。可寻址可编程寄存器保持等待状态值，表示与不同地址范围对应的不同等待状态数。响应于由数字处理器断言的外围设备的断言地址的电路产生由保持在可寻址可编程寄存器之一中的值所表示的等待状态数量，该可寻址的可编程寄存器对应于其中发出有效地址的地址范围中的一个，从而容纳外围设备的通信响应周期不同。

4. 发明授权

US5765218A Address generating circuit for generating addresses separated by a prescribed step value in circular addressing 失效
标题翻译：地址产生电路，用于在循环寻址中产生由规定步长值分隔的地址
公开(公告)号：US5765218A
公开(公告)日：1998-06-09
申请号：US402224
申请日：1995-03-10
申请人： Yuji Ozawa , Shigeshi Abiko , Frederic Boutaud
发明人： Yuji Ozawa , Shigeshi Abiko , Frederic Boutaud
IPC分类号： G06F9/34 , G06F5/10 , G06F9/345 , G06F9/355 , G06F12/02
CPC分类号： G06F5/10 , G06F9/30065 , G06F9/345 , G06F9/3552
摘要： An address generating circuit of simple configuration for circular addressing. A bit isolating circuit 304 extracts an index from an input address. When a step value input to an adder 302 is positive, an index generating circuit subtracts the sum of the index and step value from a block size of a memory region. Depending on the subtraction result, an output which is either the sum of the index and step value or the subtraction result is provided as a new index. When the step value is negative, the index and step value are added. Depending on the addition result, an output which is either the sum of the index, step value, and capacity of the memory region or the addition result is provided as a new index. A bit multiplexer 314 generates the next address from the new index and an address.
摘要翻译：一种用于循环寻址的简单配置的地址生成电路。位隔离电路304从输入地址提取索引。当输入到加法器302的阶跃值为正时，索引产生电路从存储区域的块大小中减去索引和步长值之和。根据减法结果，提供作为索引和步长值的总和或减法结果的输出作为新的索引。当步数值为负时，添加索引和步长值。根据加法结果，提供作为索引，步长值和存储区域的容量或相加结果之和的输出作为新的索引。位复用器314从新索引和地址生成下一个地址。

5. 发明授权

US5319792A Modem having first and second registers enabling both to concurrently receive identical information in one context and disabling one to retain the information in a next context 失效
标题翻译：调制解调器具有第一和第二寄存器，使得能够在一个上下文中同时接收相同的信息，并且禁止在下一个上下文中保留信息
公开(公告)号：US5319792A
公开(公告)日：1994-06-07
申请号：US958887
申请日：1992-10-09
申请人： Peter N. Ehlig , Frederic Boutaud , James F. Hollander
发明人： Peter N. Ehlig , Frederic Boutaud , James F. Hollander
IPC分类号： G01R31/3185 , G06F7/544 , G06F9/30 , G06F9/302 , G06F9/46 , G06F11/267 , G06F11/273 , G06F11/36
CPC分类号： G06F11/3652 , G01R31/318536 , G06F11/2236 , G06F7/544 , G06F9/30014 , G06F9/30021 , G06F9/30101 , G06F9/462 , G01R31/318505 , G06F11/2733 , G06F11/3648
摘要： A modem includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.
摘要翻译：调制解调器包括响应于上下文信号的电子处理器，并且可在由上下文信号识别的备选处理环境中操作。第一和第二寄存器连接到电子处理器以参与一个处理上下文，同时保留来自另一个处理环境的信息直到返回。上下文切换电路连接到第一和第二寄存器，并且操作以根据处理上下文选择性地控制寄存器到电子处理器的输出和输出操作。还公开了其他装置，系统和方法。

6. 发明授权

US5182795A Process and device for graphically drawing point by point a closed curve of the second order 失效
标题翻译：用于图形绘制二阶关闭曲线的过程和设备
公开(公告)号：US5182795A
公开(公告)日：1993-01-26
申请号：US168711
申请日：1988-03-16
申请人： Frederic Boutaud , Gerard Chauvel
发明人： Frederic Boutaud , Gerard Chauvel
IPC分类号： G06T11/20
CPC分类号： G06T11/203
摘要： A device including a screen memory (53) for storing the data relating to the points of a screen on which the curve is to be drawn. A point processor (21) modifies the data stored in the screen memory (53) at the positions of said screen memory corresponding to the points of the curve to be drawn. An address processor (20) adapted to control the access to the screen memory (53), the operation of the processor (21) and the transfers of data between the point processor (21) and the screen memory (53) so as to ensure the modification of its content as a function of the line to be drawn. A CROM memory (22) containing instructions relating to the changing of the reference of U, V relative coordinates of each octant change and instructions relating to the point by point drawings of portions of curves contained in each of the octants covered by the arc of a curve to be drawn.
摘要翻译：一种包括屏幕存储器（53）的装置，用于存储与要绘制曲线的屏幕的点有关的数据。点处理器（21）在与要绘制的曲线的点对应的所述屏幕存储器的位置处修改存储在屏幕存储器（53）中的数据。一种适于控制对屏幕存储器（53）的访问，处理器（21）的操作和点处理器（21）和屏幕存储器（53）之间的数据传送的地址处理器（20），以便确保将其内容的修改作为要绘制的行的函数。一个CROM存储器（22），其包含关于改变每个八分圆变化的U，V相对坐标的参考的指令，以及与逐点绘图有关的指令，该指令包含在由要绘制的曲线

7. 发明授权

US06732235B1 Cache memory system and method for a digital signal processor 有权
标题翻译：用于数字信号处理器的缓存存储器系统和方法
公开(公告)号：US06732235B1
公开(公告)日：2004-05-04
申请号：US09707239
申请日：2000-11-06
申请人： Paul D. Krivacek , Jørn Sørensen , Frederic Boutaud
发明人： Paul D. Krivacek , Jørn Sørensen , Frederic Boutaud
IPC分类号： G06F1200
CPC分类号： G06F15/7846 , G06F12/0862 , G06F13/14
摘要： A digital signal processing system includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masters each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention. The system further includes a cache memory system allowing one process to perform real-time digital signal processing according to a modifiable program stored in a modifiable non-volatile memory by temporarily loading portions of the program into a fast, local memory.
摘要翻译：数字信号处理系统包括多个处理器，以及一个或多个共享外设，例如存储器。该架构包括多个总线主机，每个连接到自己的总线。还有多个总线从站，每个都连接到自己的总线。总线仲裁模块选择性地互连总线，使得当多个总线主机各访问不同的总线从机时，不发生阻塞，并且当多个总线主机各访问同一总线从机时，避免了带宽的不足。该架构由总线仲裁方法支持，包括基于中断的方法的分层应用，分配的时隙旋转方法和循环方法，其避免在总线争用的长时间期间的带宽缺乏和锁定。该系统还包括高速缓冲存储器系统，其允许一个过程通过将程序的一部分临时加载到快速本地存储器中，根据存储在可修改的非易失性存储器中的可修改程序来执行实时数字信号处理。

8. 发明授权

US06249859B1 IC with wait state registers 失效
标题翻译： IC等待状态寄存器
公开(公告)号：US06249859B1
公开(公告)日：2001-06-19
申请号：US09430970
申请日：1999-11-01
申请人： Frederic Boutaud , Peter N. Ehlig
发明人： Frederic Boutaud , Peter N. Ehlig
IPC分类号： G06F1500
CPC分类号： G01R31/318536 , G01R31/318505 , G06F9/30 , G06F9/30058 , G06F9/30072 , G06F9/30094 , G06F9/325 , G06F11/2733 , G06F11/3648 , G06F11/3652
摘要： A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.
摘要翻译：数据处理设备与具有接收者和不同通信响应周期的外围设备一起使用。数据处理装置包括数字处理器，其适于通过断言每个所选择的外围设备的地址来选择不同的外围设备。可寻址可编程寄存器保持等待状态值，表示与不同地址范围对应的不同等待状态数。响应于由数字处理器断言的外围设备的断言地址的电路产生由保持在可寻址可编程寄存器之一中的值所表示的等待状态数量，该可寻址的可编程寄存器对应于其中发出有效地址的地址范围中的一个，从而容纳外围设备的通信响应周期不同。

9. 发明授权

US06240504B1 Process of operating a microprocessor to change wait states 失效
标题翻译：操作微处理器来改变等待状态的过程
公开(公告)号：US06240504B1
公开(公告)日：2001-05-29
申请号：US09431502
申请日：1999-11-01
申请人： Frederic Boutaud , Peter N Ehlig
发明人： Frederic Boutaud , Peter N Ehlig
IPC分类号： G06F1500
CPC分类号： G01R31/318536 , G01R31/318505 , G06F9/30 , G06F9/30058 , G06F9/30072 , G06F9/30094 , G06F9/325 , G06F11/2733 , G06F11/3648 , G06F11/3652
摘要： A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.
摘要翻译：数据处理设备与具有接收者和不同通信响应周期的外围设备一起使用。数据处理装置包括数字处理器，其适于通过断言每个所选择的外围设备的地址来选择不同的外围设备。可寻址可编程寄存器保持等待状态值，表示与不同地址范围对应的不同等待状态数。响应于由数字处理器断言的外围设备的断言地址的电路产生由保持在可寻址可编程寄存器之一中的值所表示的等待状态数量，该可寻址的可编程寄存器对应于其中发出有效地址的地址范围中的一个，从而容纳外围设备的通信响应周期不同。

10. 发明授权

US6134578A Data processing device and method of operation with context switching 失效
标题翻译：数据处理装置及操作方法与上下文切换
公开(公告)号：US6134578A
公开(公告)日：2000-10-17
申请号：US617673
申请日：1996-05-02
申请人： Peter N. Ehlig , Frederic Boutaud , James F. Hollander
发明人： Peter N. Ehlig , Frederic Boutaud , James F. Hollander
IPC分类号： G01R31/3185 , G06F7/544 , G06F9/30 , G06F9/302 , G06F9/46 , G06F11/267 , G06F11/273 , G06F11/36 , G06F9/00
CPC分类号： G06F11/3652 , G01R31/318536 , G06F11/2236 , G06F7/544 , G06F9/30014 , G06F9/30021 , G06F9/30101 , G06F9/462 , G01R31/318505 , G06F11/2733 , G06F11/3648
摘要： A data processing device includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.
摘要翻译：数据处理设备包括响应于上下文信号的电子处理器，并且可在由上下文信号识别的备选处理环境中操作。第一和第二寄存器连接到电子处理器以参与一个处理上下文，同时保留来自另一个处理环境的信息直到返回。上下文切换电路连接到第一和第二寄存器，并且操作以根据处理上下文选择性地控制寄存器到电子处理器的输出和输出操作。还公开了其他装置，系统和方法。

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