专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090189665A1 SCHMITT-TRIGGER-BASED LEVEL DETECTION CIRCUIT 有权
标题翻译：基于SCHMITT-TRIGGER的电平检测电路
公开(公告)号：US20090189665A1
公开(公告)日：2009-07-30
申请号：US12357965
申请日：2009-01-22
申请人： JENG-HUANG WU , SHENG-HUA CHEN
发明人： JENG-HUANG WU , SHENG-HUA CHEN
IPC分类号： H03K3/00
CPC分类号： H03K3/3565 , H03K5/082
摘要： A Schmitt trigger includes A first PMOS transistors having the drains and sources thereof serially connected and coupled between a voltage source and an output end, and having gates thereof coupled to an input end; B first NMOS transistors having the drains and sources thereof serially connected and coupled between the output end and ground, and having gates thereof coupled to the input end; C second PMOS transistors, each being coupled between ground and a node between the drain and the source of the first PMOS transistors and having the gate thereof coupled to the output end; and D second NMOS transistors, each being coupled between the voltage source and a node between the drain and the source of the first NMOS transistors and having the gate thereof coupled to the output end. A is greater than 2 and C, and B is greater than 2 and D.
摘要翻译：施密特触发器包括：第一PMOS晶体管，其漏极和源极串联连接并耦合在电压源和输出端之间，并且其栅极耦合到输入端; B第一NMOS晶体管，其漏极和源极串联连接并耦合在输出端和地之间，并且其栅极耦合到输入端; C个第二PMOS晶体管，每个PMOS晶体管分别耦合在地与第一PMOS晶体管的漏极和源极之间的节点之间，并且其栅极耦合到输出端; 和D个第二NMOS晶体管，每个都连接在电压源和第一NMOS晶体管的漏极和源极之间的节点之间，并且其栅极耦合到输出端。 A大于2，C大于2，D大于2。

2. 发明授权

US07465970B2 Common pass gate layout of a D flip flop 有权
标题翻译： D触发器的公共通道布局
公开(公告)号：US07465970B2
公开(公告)日：2008-12-16
申请号：US11382700
申请日：2006-05-10
申请人： Jeng-Huang Wu , Chiung-Yu Feng , Chien-Chih Huang , Yu-Wen Tsai
发明人： Jeng-Huang Wu , Chiung-Yu Feng , Chien-Chih Huang , Yu-Wen Tsai
IPC分类号： H01L27/02 , H01L27/10
CPC分类号： H01L27/0207
摘要： A semiconductor layout includes a p substrate, a first semiconductor cell formed over the p substrate, and a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell. A total height of the first semiconductor cell and the second semiconductor cell is twice a height of a standard semiconductor cell, and the height of the second semiconductor cell is adjusted according to the height of the first semiconductor cell.
摘要翻译：半导体布局包括p基板，在p基板上形成的第一半导体单元，以及形成在与p基板相邻的第一半导体单元上的第二半导体单元。第一半导体单元和第二半导体单元的总高度是标准半导体单元的高度的两倍，并且根据第一半导体单元的高度来调整第二半导体单元的高度。

3. 发明申请

US20080022245A1 LAYOUT ARCHITECTURE HAVING HIGH-PERFORMANCE AND HIGH-DENSITY DESIGN 失效
标题翻译：具有高性能和高密度设计的布局架构
公开(公告)号：US20080022245A1
公开(公告)日：2008-01-24
申请号：US11560838
申请日：2006-11-17
申请人： Yu-Wen Tsai , Jeng-Huang Wu
发明人： Yu-Wen Tsai , Jeng-Huang Wu
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , H01L27/11807
摘要： A layout architecture having high-performance and high-density design used in a standard cell integrated circuit is provided. The layout architecture includes a substrate, a first conductor, a second conductor, a third conductor, a fourth conductor, a first device region, a second device region, a third device region and a forth device region. The first device region is arranged adjacent to the first conductor on the substrate. The second device region is arranged adjacent to the first device region on the substrate and is arranged beneath the second conductor. The third device region is arranged adjacent to the second device region on the substrate and is arranged beneath the third conductor. The forth device region is arranged between the third device region and the forth conductor on the substrate.
摘要翻译：提供了在标准单元集成电路中使用的具有高性能和高密度设计的布局架构。布局架构包括衬底，第一导体，第二导体，第三导体，第四导体，第一器件区域，第二器件区域，第三器件区域和第四器件区域。第一器件区域布置成与衬底上的第一导体相邻。第二器件区域布置成与衬底上的第一器件区域相邻并且布置在第二导体的下方。第三器件区域布置成与衬底上的第二器件区域相邻并且布置在第三导体的下方。第四器件区域布置在衬底上的第三器件区域和第四导体之间。

4. 发明申请

US20070210857A1 Power Gating Circuit of a Signal Processing System 失效
标题翻译：信号处理系统的电源门控电路
公开(公告)号：US20070210857A1
公开(公告)日：2007-09-13
申请号：US11308151
申请日：2006-03-08
申请人： Jeng-Huang Wu , Yi-Hwa Chang , Shang-Chih Hsieh
发明人： Jeng-Huang Wu , Yi-Hwa Chang , Shang-Chih Hsieh
IPC分类号： G05F1/10
CPC分类号： G05F1/46
摘要： A power gating circuit of a signal processing system includes a low dropout linear regulator, a control circuit, and an output circuit. The low dropout linear regulator includes a first transistor, an operational amplifier, a first resistor, a second resistor, and an output end. The output circuit includes a fourth transistor and a step-down circuit. The control circuit controls output voltage of the output circuit according to a control signal.
摘要翻译：信号处理系统的电源门控电路包括低压差线性稳压器，控制电路和输出电路。低压降线性稳压器包括第一晶体管，运算放大器，第一电阻器，第二电阻器和输出端。输出电路包括第四晶体管和降压电路。控制电路根据控制信号控制输出电路的输出电压。

5. 发明申请

US20050068069A1 INPUT/OUTPUT BUFFER 有权
标题翻译：输入/输出缓冲器
公开(公告)号：US20050068069A1
公开(公告)日：2005-03-31
申请号：US10673391
申请日：2003-09-30
申请人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
发明人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
IPC分类号： H03K19/003 , H03B1/00
CPC分类号： H03K19/00315
摘要： An input/output buffer. An input/output circuit has a transmission terminal coupled to an I/O pad, and a floating N-well region. A P-gate control circuit conveys the second gate control signal to the gate of the first PMOS transistor. A feedback detection device is coupled between the transmission terminal and an N-well control circuit to output a feedback signal according to an input voltage at the I/O pad. The N-well control circuit adjusts the voltage level at the N-well region of the first PMOS transistor according to the feedback signal output from the feedback detection device.
摘要翻译：一个输入/输出缓冲区。输入/输出电路具有耦合到I / O焊盘和浮动N阱区的传输端。 P栅极控制电路将第二栅极控制信号传送到第一PMOS晶体管的栅极。反馈检测装置耦合在传输终端和N阱控制电路之间，以根据I / O焊盘的输入电压输出反馈信号。 N阱控制电路根据从反馈检测装置输出的反馈信号，调整第一PMOS晶体管的N阱区域的电压电平。

6. 发明授权

US5974476A On-chip input/output device having programmable I/O unit being configured based upon internal configuration circuit 失效
标题翻译：具有基于内部配置电路配置的可编程I / O单元的片上输入/输出装置
公开(公告)号：US5974476A
公开(公告)日：1999-10-26
申请号：US989287
申请日：1997-12-12
申请人： Tin-Hao Lin , Jeng-Huang Wu
发明人： Tin-Hao Lin , Jeng-Huang Wu
IPC分类号： G01R31/3181 , H03K19/0185 , G06F13/14 , G01R31/3187
CPC分类号： H03K19/018585 , G01R31/3181
摘要： An input/output (I/O) device with programmable I/O characteristics is provided for use on an integrated circuit to serve as a communication interface whose input/output characteristics can be set through programmable means to be matched to the external circuitry to which the IC chip is connected for use. This allows the IC chip on which the I/O device is provided to be matched for use with various kinds of external systems. Further, the I/O device can also be provided with a self-control feature that can detect whether the I/O characteristics of the I/O device are matched to the external circuitry and, if not, automatically set the I/O device to the required I/O characteristic. The I/O device can prevent an IC chip from being discarded due to a mismatch in the I/O characteristics with the external circuitry to which the IC chip is connected for use.
摘要翻译：提供具有可编程I / O特性的输入/输出（I / O）器件用于集成电路，用作通信接口，其输入/输出特性可通过可编程手段设置为与外部电路匹配， IC芯片连接使用。这允许提供I / O设备的IC芯片与各种外部系统配合使用。此外，I / O设备还可以具有可以检测I / O设备的I / O特性是否与外部电路匹配的自控功能，如果不是，I / O设备自动设置I / O设备到所需的I / O特性。由于I / O特性与IC芯片连接使用的外部电路不匹配，因此I / O设备可以防止IC芯片被丢弃。

7. 发明申请

US20090251185A1 DATA RETENTION DEVICE FOR MULTIPLE POWER DOMAINS 审中-公开
标题翻译：用于多个电源域的数据保持设备
公开(公告)号：US20090251185A1
公开(公告)日：2009-10-08
申请号：US12416380
申请日：2009-04-01
申请人： JENG-HUANG WU , CHIH-WEN YANG
发明人： JENG-HUANG WU , CHIH-WEN YANG
IPC分类号： H03K3/289
CPC分类号： H03K3/0375 , G06F1/3203 , H03K3/35625
摘要： A data retention device includes a first latch disposed between a data input terminal and a data output terminal for storing a data signal received from the data input terminal and transmitting the data signal through a data forward path to the data output terminal according to a clock signal in an operational mode; a second latch disposed in a branch of the data forward path between the first latch and the data output terminal for receiving the data signal in the operational mode and retaining the data signal in a sleep mode; and a first tri-state buffer disposed in the data forward path between the first latch and the branched second latch and enabled to conduct the data forward path in the operational mode and disabled to cut off the data forward path in the sleep mode according to a data retention signal.
摘要翻译：数据保持装置包括设置在数据输入端和数据输出端之间的第一锁存器，用于存储从数据输入端接收的数据信号，并根据时钟信号通过数据转发路径将数据信号发送到数据输出端在操作模式下设置在第一锁存器和数据输出端子之间的数据前向路径的分支中的第二锁存器，用于在操作模式下接收数据信号并将数据信号保持在睡眠模式; 以及第一三态缓冲器，其设置在第一锁存器和分支第二锁存器之间的数据前向路径中，并且能够在操作模式下传导数据前向路径，并且禁用该功能以根据睡眠模式切断数据转发路径数据保留信号。

8. 发明申请

US20070272947A1 Low Power Consuming Semiconductor Device 审中-公开
标题翻译：低功耗半导体器件
公开(公告)号：US20070272947A1
公开(公告)日：2007-11-29
申请号：US11382487
申请日：2006-05-10
申请人： Jeng-Huang Wu , Shang-Chih Hsieh , Yu-Wen Tsai
发明人： Jeng-Huang Wu , Shang-Chih Hsieh , Yu-Wen Tsai
IPC分类号： H01L27/10
CPC分类号： H01L27/0207
摘要： A low power consuming semiconductor device comprises a p substrate, a first semiconductor cell formed over the p substrate, a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell, and a tap cell for coupling a power pin to n-well structures of the first semiconductor cell and the second semiconductor cell, and for coupling a ground pin to the p substrate. A total height of the first semiconductor cell and the second semiconductor cell is twice a height of a standard semiconductor cell, and the height of the second semiconductor cell is adjusted according to the height of the first semiconductor cell.
摘要翻译：一种低功率消耗半导体器件包括ap衬底，形成在p衬底上的第一半导体单元，形成在与p型衬底相邻的第一半导体单元上的第二半导体单元，以及用于将电源引脚耦合到n阱结构的抽头单元的第一半导体单元和第二半导体单元，并且用于将接地引脚耦合到p基板。第一半导体单元和第二半导体单元的总高度是标准半导体单元的高度的两倍，并且根据第一半导体单元的高度来调整第二半导体单元的高度。

9. 发明授权

US08169068B2 IO cell with multiple IO ports and related techniques for layout area saving 有权
标题翻译：具有多个IO端口的IO单元和相关技术，用于布局区域的保存
公开(公告)号：US08169068B2
公开(公告)日：2012-05-01
申请号：US12697582
申请日：2010-02-01
申请人： Jeng-Huang Wu , Hung-Yi Chang , Chun Huang
发明人： Jeng-Huang Wu , Hung-Yi Chang , Chun Huang
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/02166 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/49431 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01033 , H01L2924/01046 , H01L2924/01055 , H01L2924/01082 , H01L2924/01084 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： An IO cell with multiple IO ports and related techniques are provided. The IO cell has a plurality of IO ports for transmitting signal of a same IO pin, and each IO port corresponds to a predetermined region for containing an IO pad, wherein at least one of the plural predetermined regions of the plural IO ports partially overlaps with active circuit layout region of the IO cell. In a chip, if a given IO cell has a predetermined region of an IO port overlapping an IO pad location of another adjacent IO cell, then a predetermined region of another IO port is selected for implementing an IO pad of the given IO cell, such that the IO cells can be arranged more compactly for chip layout area saving.
摘要翻译：提供了具有多个IO端口和相关技术的IO单元。 IO单元具有用于发送相同IO引脚的信号的多个IO端口，并且每个IO端口对应于用于容纳IO垫的预定区域，其中多个IO端口的多个预定区域中的至少一个部分地与 IO单元的有源电路布局区域。在芯片中，如果给定IO单元具有与另一相邻IO单元的IO垫位置重叠的IO端口的预定区域，则选择另一IO端口的预定区域以实现给定IO单元的IO垫，可以更紧凑地布置IO单元，以节省芯片布局面积。

10. 发明授权

US07707521B2 Layout architecture having high-performance and high-density design 失效
标题翻译：布局架构具有高性能和高密度设计
公开(公告)号：US07707521B2
公开(公告)日：2010-04-27
申请号：US11560838
申请日：2006-11-17
申请人： Yu-Wen Tsai , Jeng-Huang Wu
发明人： Yu-Wen Tsai , Jeng-Huang Wu
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , H01L27/11807
摘要： A layout architecture having high-performance and high-density design used in a standard cell integrated circuit is provided. The layout architecture includes a substrate, a first conductor, a second conductor, a third conductor, a fourth conductor, a first device region, a second device region, a third device region and a forth device region. The first device region is arranged adjacent to the first conductor on the substrate. The second device region is arranged adjacent to the first device region on the substrate and is arranged beneath the second conductor. The third device region is arranged adjacent to the second device region on the substrate and is arranged beneath the third conductor. The fourth device region is arranged between the third device region and the fourth conductor on the substrate.
摘要翻译：提供了在标准单元集成电路中使用的具有高性能和高密度设计的布局架构。布局架构包括衬底，第一导体，第二导体，第三导体，第四导体，第一器件区域，第二器件区域，第三器件区域和第四器件区域。第一器件区域布置成与衬底上的第一导体相邻。第二器件区域布置成与衬底上的第一器件区域相邻并且布置在第二导体的下方。第三器件区域布置成与衬底上的第二器件区域相邻并且布置在第三导体的下方。第四器件区域布置在衬底上的第三器件区域和第四导体之间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式