专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090251185A1 DATA RETENTION DEVICE FOR MULTIPLE POWER DOMAINS 审中-公开
标题翻译：用于多个电源域的数据保持设备
公开(公告)号：US20090251185A1
公开(公告)日：2009-10-08
申请号：US12416380
申请日：2009-04-01
申请人： JENG-HUANG WU , CHIH-WEN YANG
发明人： JENG-HUANG WU , CHIH-WEN YANG
IPC分类号： H03K3/289
CPC分类号： H03K3/0375 , G06F1/3203 , H03K3/35625
摘要： A data retention device includes a first latch disposed between a data input terminal and a data output terminal for storing a data signal received from the data input terminal and transmitting the data signal through a data forward path to the data output terminal according to a clock signal in an operational mode; a second latch disposed in a branch of the data forward path between the first latch and the data output terminal for receiving the data signal in the operational mode and retaining the data signal in a sleep mode; and a first tri-state buffer disposed in the data forward path between the first latch and the branched second latch and enabled to conduct the data forward path in the operational mode and disabled to cut off the data forward path in the sleep mode according to a data retention signal.
摘要翻译：数据保持装置包括设置在数据输入端和数据输出端之间的第一锁存器，用于存储从数据输入端接收的数据信号，并根据时钟信号通过数据转发路径将数据信号发送到数据输出端在操作模式下设置在第一锁存器和数据输出端子之间的数据前向路径的分支中的第二锁存器，用于在操作模式下接收数据信号并将数据信号保持在睡眠模式; 以及第一三态缓冲器，其设置在第一锁存器和分支第二锁存器之间的数据前向路径中，并且能够在操作模式下传导数据前向路径，并且禁用该功能以根据睡眠模式切断数据转发路径数据保留信号。

2. 发明申请

US20090189665A1 SCHMITT-TRIGGER-BASED LEVEL DETECTION CIRCUIT 有权
标题翻译：基于SCHMITT-TRIGGER的电平检测电路
公开(公告)号：US20090189665A1
公开(公告)日：2009-07-30
申请号：US12357965
申请日：2009-01-22
申请人： JENG-HUANG WU , SHENG-HUA CHEN
发明人： JENG-HUANG WU , SHENG-HUA CHEN
IPC分类号： H03K3/00
CPC分类号： H03K3/3565 , H03K5/082
摘要： A Schmitt trigger includes A first PMOS transistors having the drains and sources thereof serially connected and coupled between a voltage source and an output end, and having gates thereof coupled to an input end; B first NMOS transistors having the drains and sources thereof serially connected and coupled between the output end and ground, and having gates thereof coupled to the input end; C second PMOS transistors, each being coupled between ground and a node between the drain and the source of the first PMOS transistors and having the gate thereof coupled to the output end; and D second NMOS transistors, each being coupled between the voltage source and a node between the drain and the source of the first NMOS transistors and having the gate thereof coupled to the output end. A is greater than 2 and C, and B is greater than 2 and D.
摘要翻译：施密特触发器包括：第一PMOS晶体管，其漏极和源极串联连接并耦合在电压源和输出端之间，并且其栅极耦合到输入端; B第一NMOS晶体管，其漏极和源极串联连接并耦合在输出端和地之间，并且其栅极耦合到输入端; C个第二PMOS晶体管，每个PMOS晶体管分别耦合在地与第一PMOS晶体管的漏极和源极之间的节点之间，并且其栅极耦合到输出端; 和D个第二NMOS晶体管，每个都连接在电压源和第一NMOS晶体管的漏极和源极之间的节点之间，并且其栅极耦合到输出端。 A大于2，C大于2，D大于2。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式