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1. 发明申请

US20070272947A1 Low Power Consuming Semiconductor Device 审中-公开
标题翻译：低功耗半导体器件
公开(公告)号：US20070272947A1
公开(公告)日：2007-11-29
申请号：US11382487
申请日：2006-05-10
申请人： Jeng-Huang Wu , Shang-Chih Hsieh , Yu-Wen Tsai
发明人： Jeng-Huang Wu , Shang-Chih Hsieh , Yu-Wen Tsai
IPC分类号： H01L27/10
CPC分类号： H01L27/0207
摘要： A low power consuming semiconductor device comprises a p substrate, a first semiconductor cell formed over the p substrate, a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell, and a tap cell for coupling a power pin to n-well structures of the first semiconductor cell and the second semiconductor cell, and for coupling a ground pin to the p substrate. A total height of the first semiconductor cell and the second semiconductor cell is twice a height of a standard semiconductor cell, and the height of the second semiconductor cell is adjusted according to the height of the first semiconductor cell.
摘要翻译：一种低功率消耗半导体器件包括ap衬底，形成在p衬底上的第一半导体单元，形成在与p型衬底相邻的第一半导体单元上的第二半导体单元，以及用于将电源引脚耦合到n阱结构的抽头单元的第一半导体单元和第二半导体单元，并且用于将接地引脚耦合到p基板。第一半导体单元和第二半导体单元的总高度是标准半导体单元的高度的两倍，并且根据第一半导体单元的高度来调整第二半导体单元的高度。

2. 发明授权

US07465970B2 Common pass gate layout of a D flip flop 有权
标题翻译： D触发器的公共通道布局
公开(公告)号：US07465970B2
公开(公告)日：2008-12-16
申请号：US11382700
申请日：2006-05-10
申请人： Jeng-Huang Wu , Chiung-Yu Feng , Chien-Chih Huang , Yu-Wen Tsai
发明人： Jeng-Huang Wu , Chiung-Yu Feng , Chien-Chih Huang , Yu-Wen Tsai
IPC分类号： H01L27/02 , H01L27/10
CPC分类号： H01L27/0207
摘要： A semiconductor layout includes a p substrate, a first semiconductor cell formed over the p substrate, and a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell. A total height of the first semiconductor cell and the second semiconductor cell is twice a height of a standard semiconductor cell, and the height of the second semiconductor cell is adjusted according to the height of the first semiconductor cell.
摘要翻译：半导体布局包括p基板，在p基板上形成的第一半导体单元，以及形成在与p基板相邻的第一半导体单元上的第二半导体单元。第一半导体单元和第二半导体单元的总高度是标准半导体单元的高度的两倍，并且根据第一半导体单元的高度来调整第二半导体单元的高度。

3. 发明申请

US20080022245A1 LAYOUT ARCHITECTURE HAVING HIGH-PERFORMANCE AND HIGH-DENSITY DESIGN 失效
标题翻译：具有高性能和高密度设计的布局架构
公开(公告)号：US20080022245A1
公开(公告)日：2008-01-24
申请号：US11560838
申请日：2006-11-17
申请人： Yu-Wen Tsai , Jeng-Huang Wu
发明人： Yu-Wen Tsai , Jeng-Huang Wu
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , H01L27/11807
摘要： A layout architecture having high-performance and high-density design used in a standard cell integrated circuit is provided. The layout architecture includes a substrate, a first conductor, a second conductor, a third conductor, a fourth conductor, a first device region, a second device region, a third device region and a forth device region. The first device region is arranged adjacent to the first conductor on the substrate. The second device region is arranged adjacent to the first device region on the substrate and is arranged beneath the second conductor. The third device region is arranged adjacent to the second device region on the substrate and is arranged beneath the third conductor. The forth device region is arranged between the third device region and the forth conductor on the substrate.
摘要翻译：提供了在标准单元集成电路中使用的具有高性能和高密度设计的布局架构。布局架构包括衬底，第一导体，第二导体，第三导体，第四导体，第一器件区域，第二器件区域，第三器件区域和第四器件区域。第一器件区域布置成与衬底上的第一导体相邻。第二器件区域布置成与衬底上的第一器件区域相邻并且布置在第二导体的下方。第三器件区域布置成与衬底上的第二器件区域相邻并且布置在第三导体的下方。第四器件区域布置在衬底上的第三器件区域和第四导体之间。

4. 发明授权

US07707521B2 Layout architecture having high-performance and high-density design 失效
标题翻译：布局架构具有高性能和高密度设计
公开(公告)号：US07707521B2
公开(公告)日：2010-04-27
申请号：US11560838
申请日：2006-11-17
申请人： Yu-Wen Tsai , Jeng-Huang Wu
发明人： Yu-Wen Tsai , Jeng-Huang Wu
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , H01L27/11807
摘要： A layout architecture having high-performance and high-density design used in a standard cell integrated circuit is provided. The layout architecture includes a substrate, a first conductor, a second conductor, a third conductor, a fourth conductor, a first device region, a second device region, a third device region and a forth device region. The first device region is arranged adjacent to the first conductor on the substrate. The second device region is arranged adjacent to the first device region on the substrate and is arranged beneath the second conductor. The third device region is arranged adjacent to the second device region on the substrate and is arranged beneath the third conductor. The fourth device region is arranged between the third device region and the fourth conductor on the substrate.
摘要翻译：提供了在标准单元集成电路中使用的具有高性能和高密度设计的布局架构。布局架构包括衬底，第一导体，第二导体，第三导体，第四导体，第一器件区域，第二器件区域，第三器件区域和第四器件区域。第一器件区域布置成与衬底上的第一导体相邻。第二器件区域布置成与衬底上的第一器件区域相邻并且布置在第二导体的下方。第三器件区域布置成与衬底上的第二器件区域相邻并且布置在第三导体的下方。第四器件区域布置在衬底上的第三器件区域和第四导体之间。

5. 发明申请

US20070262349A1 Common Pass Gate Layout of a D Flip Flop 有权
标题翻译： D触发器的普通通道布局
公开(公告)号：US20070262349A1
公开(公告)日：2007-11-15
申请号：US11382700
申请日：2006-05-10
申请人： Jeng-Huang Wu , Chiung-Yu Feng , Chien-Chih Huang , Yu-Wen Tsai
发明人： Jeng-Huang Wu , Chiung-Yu Feng , Chien-Chih Huang , Yu-Wen Tsai
IPC分类号： H01L27/10
CPC分类号： H01L27/0207
摘要： A semiconductor layout includes a p substrate, a first semiconductor cell formed over the p substrate, and a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell. A total height of the first semiconductor cell and the second semiconductor cell is twice a height of a standard semiconductor cell, and the height of the second semiconductor cell is adjusted according to the height of the first semiconductor cell.
摘要翻译：半导体布局包括p基板，在p基板上形成的第一半导体单元，以及形成在与p基板相邻的第一半导体单元上的第二半导体单元。第一半导体单元和第二半导体单元的总高度是标准半导体单元的高度的两倍，并且根据第一半导体单元的高度来调整第二半导体单元的高度。

6. 发明授权

US07764101B2 Schmitt-trigger-based level detection circuit 有权
标题翻译：基于施密特触发的电平检测电路
公开(公告)号：US07764101B2
公开(公告)日：2010-07-27
申请号：US12357965
申请日：2009-01-22
申请人： Jeng-Huang Wu , Sheng-Hua Chen
发明人： Jeng-Huang Wu , Sheng-Hua Chen
IPC分类号： H03K3/12
CPC分类号： H03K3/3565 , H03K5/082
摘要： A Schmitt trigger includes A first PMOS transistors having the drains and sources thereof serially connected and coupled between a voltage source and an output end, and having gates thereof coupled to an input end; B first NMOS transistors having the drains and sources thereof serially connected and coupled between the output end and ground, and having gates thereof coupled to the input end; C second PMOS transistors, each being coupled between ground and a node between the drain and the source of the first PMOS transistors and having the gate thereof coupled to the output end; and D second NMOS transistors, each being coupled between the voltage source and a node between the drain and the source of the first NMOS transistors and having the gate thereof coupled to the output end. A is greater than 2 and C, and B is greater than 2 and D.
摘要翻译：施密特触发器包括：第一PMOS晶体管，其漏极和源极串联连接并耦合在电压源和输出端之间，并且其栅极耦合到输入端; B第一NMOS晶体管，其漏极和源极串联连接并耦合在输出端和地之间，并且其栅极耦合到输入端; C个第二PMOS晶体管，每个PMOS晶体管分别耦合在地与第一PMOS晶体管的漏极和源极之间的节点之间，并且其栅极耦合到输出端; 和D个第二NMOS晶体管，每个都连接在电压源和第一NMOS晶体管的漏极和源极之间的节点之间，并且其栅极耦合到输出端。 A大于2，C大于2，D大于2。

7. 发明授权

US07046493B2 Input/output buffer protection circuit 有权
标题翻译：输入/输出缓冲保护电路
公开(公告)号：US07046493B2
公开(公告)日：2006-05-16
申请号：US10735324
申请日：2003-12-12
申请人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
发明人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
IPC分类号： H02H9/00
CPC分类号： H03K19/00315 , H01L27/0266
摘要： An input/output buffer protection circuit, which comprises an I/O pad, an I/O buffer, an n-well control circuit, a gate control circuit, and a protection component. The I/O buffer includes a PMOS transistor and a NMOS transistor. The n-well control circuit is coupled to an n-well of the PMOS transistor. When an input voltage higher than a source voltage is applied, voltage at the n-well of the PMOS is increased by the n-well control circuit to the input voltage level. The gate control circuit is coupled to the gate terminal of the PMOS transistor and the input/output pad. When an input voltage higher than a source voltage is applied, voltage at the gate terminal of the PMOS is increased by the gate control circuit to the source voltage level. Wherein the gate control circuit comprises a transistor and the transistor transfers a high potential control voltage to the gate of the PMOS transistor in output mode. The protection component is coupled between the gate of the transistor and the I/O pad to generate a voltage drop down path and block the I/O pad signal from flowing back to the gate of the transistor.
摘要翻译：输入/输出缓冲器保护电路，其包括I / O焊盘，I / O缓冲器，n阱控制电路，栅极控制电路和保护部件。 I / O缓冲器包括PMOS晶体管和NMOS晶体管。 n阱控制电路耦合到PMOS晶体管的n阱。当施加高于源电压的输入电压时，PMOS的n阱处的电压由n阱控制电路增加到输入电压电平。栅极控制电路耦合到PMOS晶体管的栅极端子和输入/输出焊盘。当施加高于源极电压的输入电压时，PMOS栅极端子处的电压由栅极控制电路增加到源极电压电平。其中栅极控制电路包括晶体管，并且晶体管在输出模式下将高电位控制电压传送到PMOS晶体管的栅极。保护元件耦合在晶体管的栅极和I / O焊盘之间，以产生电压降降路径，并阻止I / O焊盘信号流回晶体管的栅极。

8. 发明申请

US20050285689A1 Crystal oscillator circuit with activation control 失效
标题翻译：晶振电路具有启动控制功能
公开(公告)号：US20050285689A1
公开(公告)日：2005-12-29
申请号：US10876083
申请日：2004-06-24
申请人： Jeng-Huang Wu , Sheng-Hua Chen
发明人： Jeng-Huang Wu , Sheng-Hua Chen
IPC分类号： H03B1/00 , H03K3/03
CPC分类号： H03K3/0307
摘要： A CMOS Pierce crystal oscillator. A clock generator with activation control, for generating a clock signal. The clock generator comprises an amplifier, a shaping circuit and a diagnostic circuit. The amplifier is capable of being coupled to an external oscillation source through an input pad and an output pad to generate an oscillating signal, the shaping circuit is capable of being coupled to the output pad, for shaping the oscillating signal to generate a clock signal, and the diagnostic circuit is capable of being coupled to the output pad, for asserting a ready signal when amplitude of the oscillating signal exceeds a predetermined portion of a full swing voltage.
摘要翻译： CMOS皮尔斯晶体振荡器。具有启动控制的时钟发生器，用于产生时钟信号。时钟发生器包括放大器，整形电路和诊断电路。放大器能够通过输入焊盘和输出焊盘耦合到外部振荡源以产生振荡信号，整形电路能够耦合到输出焊盘，用于整形振荡信号以产生时钟信号，并且诊断电路能够耦合到输出焊盘，用于当振荡信号的振幅超过全摆幅电压的预定部分时断言就绪信号。

9. 发明授权

US6160457A Universal crystal-oscillator input/output circuit for application-specific integrated circuit with enhanced charge device mode electrostatic discharge protection 失效
标题翻译：通用晶体振荡器输入/输出电路，用于专用集成电路，具有增强的充电器件模式静电放电保护
公开(公告)号：US6160457A
公开(公告)日：2000-12-12
申请号：US327084
申请日：1999-06-04
申请人： Jeng-Huang Wu
发明人： Jeng-Huang Wu
IPC分类号： H03B5/30 , H03B5/36 , H03B5/00
CPC分类号： H03B5/364 , H03B5/30
摘要： A universal crystal-oscillator input/output (I/O) circuit is provided for use with an ASIC (Application Specific Integrated Circuit) device, and which can help enhance the electrostatic discharge (ESD) protection on the ASIC device in Charge Device Mode (CDM). This universal crystal-oscillator I/O circuit can help reduce the total number of I/O components in the ASIC library used to construct the IC device, allowing the design and management of ASIC library to be more simplified and convenient, making ASIC more cost-effective to implement. Moreover, this universal crystal-oscillator I/O circuit can help improve the performance of the oscillator circuit, allowing ASIC designers to have more convenience and flexibility in ASIC design. It can be fast in starting oscillation and low in power consumption. In CDM ESD test, the ESD current flowing into the universal crystal-oscillator I/O circuit would be drained away through the third PMOS transistor or the third NMOS transistor, thus preventing the internal circuitry of the ASIC device from being damaged by the ESD current. This universal crystal-oscillator I/O circuit is therefore able to remove electrostatic electricity accumulated on the IC substrate in CDM ESD test, allowing the ASIC device to easily pass the CDM ESD test.
摘要翻译：提供通用晶体振荡器输入/输出（I / O）电路用于ASIC（专用集成电路）器件，并且可以有助于增强充电器模式下的ASIC器件上的静电放电（ESD）保护（ CDM）。这种通用晶体振荡器I / O电路可以帮助减少用于构建IC器件的ASIC库中的I / O组件总数，从而使ASIC库的设计和管理更加简便方便，从而使ASIC成本更高有效实施。此外，这种通用晶体振荡器I / O电路可以帮助提高振荡器电路的性能，从而允许ASIC设计人员在ASIC设计中具有更多的便利性和灵活性。启动振荡速度快，功耗低。在CDM ESD测试中，流入通用晶体振荡器I / O电路的ESD电流将通过第三个PMOS晶体管或第三个NMOS晶体管被耗尽，从而防止ASIC器件的内部电路被ESD电流损坏。因此，这种通用晶体振荡器I / O电路能够在CDM ESD测试中去除积聚在IC基板上的静电电流，从而允许ASIC器件轻松通过CDM ESD测试。

10. 发明申请

US20070210857A1 Power Gating Circuit of a Signal Processing System 失效
标题翻译：信号处理系统的电源门控电路
公开(公告)号：US20070210857A1
公开(公告)日：2007-09-13
申请号：US11308151
申请日：2006-03-08
申请人： Jeng-Huang Wu , Yi-Hwa Chang , Shang-Chih Hsieh
发明人： Jeng-Huang Wu , Yi-Hwa Chang , Shang-Chih Hsieh
IPC分类号： G05F1/10
CPC分类号： G05F1/46
摘要： A power gating circuit of a signal processing system includes a low dropout linear regulator, a control circuit, and an output circuit. The low dropout linear regulator includes a first transistor, an operational amplifier, a first resistor, a second resistor, and an output end. The output circuit includes a fourth transistor and a step-down circuit. The control circuit controls output voltage of the output circuit according to a control signal.
摘要翻译：信号处理系统的电源门控电路包括低压差线性稳压器，控制电路和输出电路。低压降线性稳压器包括第一晶体管，运算放大器，第一电阻器，第二电阻器和输出端。输出电路包括第四晶体管和降压电路。控制电路根据控制信号控制输出电路的输出电压。

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