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1. 发明申请

US20070210857A1 Power Gating Circuit of a Signal Processing System 失效
标题翻译：信号处理系统的电源门控电路
公开(公告)号：US20070210857A1
公开(公告)日：2007-09-13
申请号：US11308151
申请日：2006-03-08
申请人： Jeng-Huang Wu , Yi-Hwa Chang , Shang-Chih Hsieh
发明人： Jeng-Huang Wu , Yi-Hwa Chang , Shang-Chih Hsieh
IPC分类号： G05F1/10
CPC分类号： G05F1/46
摘要： A power gating circuit of a signal processing system includes a low dropout linear regulator, a control circuit, and an output circuit. The low dropout linear regulator includes a first transistor, an operational amplifier, a first resistor, a second resistor, and an output end. The output circuit includes a fourth transistor and a step-down circuit. The control circuit controls output voltage of the output circuit according to a control signal.
摘要翻译：信号处理系统的电源门控电路包括低压差线性稳压器，控制电路和输出电路。低压降线性稳压器包括第一晶体管，运算放大器，第一电阻器，第二电阻器和输出端。输出电路包括第四晶体管和降压电路。控制电路根据控制信号控制输出电路的输出电压。

2. 发明授权

US07414458B2 Power gating circuit of a signal processing system 失效
标题翻译：信号处理系统的电源门控电路
公开(公告)号：US07414458B2
公开(公告)日：2008-08-19
申请号：US11308151
申请日：2006-03-08
申请人： Jeng-Huang Wu , Yi-Hwa Chang , Shang-Chih Hsieh
发明人： Jeng-Huang Wu , Yi-Hwa Chang , Shang-Chih Hsieh
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F1/46
摘要： A power gating circuit of a signal processing system includes a low dropout linear regulator, a control circuit, and an output circuit. The low dropout linear regulator includes a first transistor, an operational amplifier, a first resistor, a second resistor, and an output end. The output circuit includes a fourth transistor and a step-down circuit. The control circuit controls output voltage of the output circuit according to a control signal.
摘要翻译：信号处理系统的电源门控电路包括低压差线性稳压器，控制电路和输出电路。低压降线性稳压器包括第一晶体管，运算放大器，第一电阻器，第二电阻器和输出端。输出电路包括第四晶体管和降压电路。控制电路根据控制信号控制输出电路的输出电压。

3. 发明申请

US20070272947A1 Low Power Consuming Semiconductor Device 审中-公开
标题翻译：低功耗半导体器件
公开(公告)号：US20070272947A1
公开(公告)日：2007-11-29
申请号：US11382487
申请日：2006-05-10
申请人： Jeng-Huang Wu , Shang-Chih Hsieh , Yu-Wen Tsai
发明人： Jeng-Huang Wu , Shang-Chih Hsieh , Yu-Wen Tsai
IPC分类号： H01L27/10
CPC分类号： H01L27/0207
摘要： A low power consuming semiconductor device comprises a p substrate, a first semiconductor cell formed over the p substrate, a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell, and a tap cell for coupling a power pin to n-well structures of the first semiconductor cell and the second semiconductor cell, and for coupling a ground pin to the p substrate. A total height of the first semiconductor cell and the second semiconductor cell is twice a height of a standard semiconductor cell, and the height of the second semiconductor cell is adjusted according to the height of the first semiconductor cell.
摘要翻译：一种低功率消耗半导体器件包括ap衬底，形成在p衬底上的第一半导体单元，形成在与p型衬底相邻的第一半导体单元上的第二半导体单元，以及用于将电源引脚耦合到n阱结构的抽头单元的第一半导体单元和第二半导体单元，并且用于将接地引脚耦合到p基板。第一半导体单元和第二半导体单元的总高度是标准半导体单元的高度的两倍，并且根据第一半导体单元的高度来调整第二半导体单元的高度。

4. 发明申请

US20080303573A1 DATA-RETENTION LATCH FOR SLEEP MODE APPLICATION 审中-公开
标题翻译：休眠模式应用的数据保持锁
公开(公告)号：US20080303573A1
公开(公告)日：2008-12-11
申请号：US11760871
申请日：2007-06-11
申请人： Shang-Chih Hsieh , Jeng-Huang Wu
发明人： Shang-Chih Hsieh , Jeng-Huang Wu
IPC分类号： H03K3/00 , H03K3/289
CPC分类号： H03K3/0375
摘要： A latch includes a data input terminal for receiving a data signal; a data output terminal for outputting the data signal; a first control terminal for receiving a control signal to set or reset the data signal derived from the data output terminal; a sleep signal input terminal for receiving a sleep signal to determine a sleep mode; a first logic circuit having input terminals coupled to the data input terminal, the first control terminal and the sleep signal input terminal and an output terminal coupled to the data output terminal; and a second logic circuit having input terminals coupled to the data output terminal, the first control terminal and the sleep signal input terminal and an output terminal coupled to the data input terminal; wherein the first logic circuit or the second logic circuit ignores the first control signal in response to the sleep signal when the latch is operated in the sleep mode.
摘要翻译：锁存器包括用于接收数据信号的数据输入端; 数据输出端子，用于输出数据信号; 第一控制终端，用于接收控制信号以设置或重置从数据输出端导出的数据信号; 休眠信号输入端子，用于接收休眠信号以确定睡眠模式; 第一逻辑电路，其具有耦合到数据输入端子，第一控制端子和睡眠信号输入端子的输入端子和耦合到数据输出端子的输出端子; 以及第二逻辑电路，其具有耦合到所述数据输出端子，所述第一控制端子和所述睡眠信号输入端子的输入端子以及耦合到所述数据输入端子的输出端子; 其中当所述锁存器在所述睡眠模式下操作时，所述第一逻辑电路或所述第二逻辑电路响应于所述睡眠信号而忽略所述第一控制信号。

5. 发明授权

US07797593B2 Method and apparatus for memory AC timing measurement 有权
标题翻译：存储器交流定时测量方法和装置
公开(公告)号：US07797593B2
公开(公告)日：2010-09-14
申请号：US11958710
申请日：2007-12-18
申请人： Chih-Chiang Hsu , Shang-Chih Hsieh
发明人： Chih-Chiang Hsu , Shang-Chih Hsieh
IPC分类号： G11C29/00 , G06F11/00 , G06F1/00 , G04F10/00
CPC分类号： G11C29/50 , G11C29/12 , G11C29/50012
摘要： A timing measurement circuit inside a memory chip delays balanced test signals for generating delayed test signals. Each of the delayed test signals is input a corresponding input pin of a memory subsystem of the memory chip. By adjusting delay amount of the delayed test signals, AC timing parameters of the memory subsystem are tested and measured. When the timing measurement circuit is in ring oscillation, a resolution thereof is measured.
摘要翻译：存储器芯片内的定时测量电路延迟用于产生延迟测试信号的平衡测试信号。每个延迟测试信号输入存储器芯片的存储器子系统的相应输入引脚。通过调整延迟测试信号的延迟量，对存储器子系统的交流定时参数进行测试和测量。当定时测量电路处于环形振荡时，测量其分辨率。

6. 发明授权

US08698205B2 Integrated circuit layout having mixed track standard cell 有权
标题翻译：具有混合轨道标准单元的集成电路布局
公开(公告)号：US08698205B2
公开(公告)日：2014-04-15
申请号：US13481270
申请日：2012-05-25
申请人： Jiann-Tyng Tzeng , Chih-Liang Chen , Yi-Feng Chen , Kam-Tou Sio , Shang-Chih Hsieh , Helen Shu-Hui Chang
发明人： Jiann-Tyng Tzeng , Chih-Liang Chen , Yi-Feng Chen , Kam-Tou Sio , Shang-Chih Hsieh , Helen Shu-Hui Chang
IPC分类号： H01L27/10 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119 , H01L27/082 , H01L27/102
CPC分类号： H01L27/0207 , H01L27/11807 , H01L2027/11874
摘要： An integrated circuit layout having a mixed track standard cell configuration that having a mixed track standard cell configuration that includes first well regions of a predetermined height and second well regions of a predetermined height, the first and second well regions are arranged within a substrate, first conductors and second conductors arranged and extending across regions of corresponding first and second well regions, and a plurality of standard cells in multiple rows. The standard cells include a first substantially equal to standard cell having a first cell height substantially equal to I(X+Y)+X or Y, wherein X is one half the predetermined height of the first well region, Y is one half the predetermined height of the second well region, and I is a positive integer.
摘要翻译：具有混合轨迹标准单元结构的集成电路布局具有混合轨道标准单元配置，其包括预定高度的第一阱区域和预定高度的第二阱区域，所述第一阱区域和第二阱区域布置在衬底内，首先布置并延伸穿过对应的第一和第二阱区域的区域的导体和第二导体以及多行的多个标准单元。标准单元包括第一基本上等于具有基本上等于I（X + Y）+ X或Y的第一单元高度的标准单元，其中X是第一阱区的预定高度的一半，Y是预定的第二阱区的高度，I为正整数。

7. 发明授权

US07512856B2 Register circuit, scanning register circuit utilizing register circuits and scanning method thereof 有权
标题翻译：寄存器电路，利用寄存器电路的扫描寄存器电路及其扫描方法
公开(公告)号：US07512856B2
公开(公告)日：2009-03-31
申请号：US11562424
申请日：2006-11-22
申请人： Tzu-Pin Shen , Shang-Chih Hsieh
发明人： Tzu-Pin Shen , Shang-Chih Hsieh
IPC分类号： G01R31/28
CPC分类号： G01R31/318541
摘要： The present invention discloses a register circuit. The register circuit includes a latch circuit for latching an input data to generate an output data; an input signal selecting circuit, coupled to a non-test data and a test data respectively, for selectively outputting the non-test data or the test data as the input data; a control circuit, coupled to a driving clock, for controlling the latch circuit to latch the input data as the output data according to the driving clock; and a scanning circuit, coupled to the driving clock and the latch circuit, for scanning the output data of the latch circuit to generate a scanning data according to the driving clock.
摘要翻译：本发明公开了一种寄存器电路。寄存器电路包括用于锁存输入数据以产生输出数据的锁存电路; 输入信号选择电路，分别耦合到非测试数据和测试数据，用于选择性地输出非测试数据或测试数据作为输入数据; 耦合到驱动时钟的控制电路，用于根据驱动时钟控制锁存电路锁存输入数据作为输出数据; 以及耦合到驱动时钟和锁存电路的扫描电路，用于扫描锁存电路的输出数据，以根据驱动时钟生成扫描数据。

8. 发明申请

US20080116929A1 REGISTER CIRCUIT, SCANNING REGISTER CIRCUIT UTILIZING REGISTER CIRCUITS AND SCANNING METHOD THEREOF 有权
标题翻译：寄存器电路，使用寄存器电路的扫描寄存器电路及其扫描方法
公开(公告)号：US20080116929A1
公开(公告)日：2008-05-22
申请号：US11562424
申请日：2006-11-22
申请人： Tzu-Pin Shen , Shang-Chih Hsieh
发明人： Tzu-Pin Shen , Shang-Chih Hsieh
IPC分类号： G01R31/319
CPC分类号： G01R31/318541
摘要： The present invention discloses a register circuit. The register circuit includes a latch circuit for latching an input data to generate an output data; an input signal selecting circuit, coupled to a non-test data and a test data respectively, for selectively outputting the non-test data or the test data as the input data; a control circuit, coupled to a driving clock, for controlling the latch circuit to latch the input data as the output data according to the driving clock; and a scanning circuit, coupled to the driving clock and the latch circuit, for scanning the output data of the latch circuit to generate a scanning data according to the driving clock.
摘要翻译：本发明公开了一种寄存器电路。寄存器电路包括用于锁存输入数据以产生输出数据的锁存电路; 输入信号选择电路，分别耦合到非测试数据和测试数据，用于选择性地输出非测试数据或测试数据作为输入数据; 耦合到驱动时钟的控制电路，用于根据驱动时钟控制锁存电路锁存输入数据作为输出数据; 以及耦合到驱动时钟和锁存电路的扫描电路，用于扫描锁存电路的输出数据，以根据驱动时钟生成扫描数据。

9. 发明授权

US08068349B2 Power supply architecture for structural ASIC 有权
标题翻译：结构ASIC的电源架构
公开(公告)号：US08068349B2
公开(公告)日：2011-11-29
申请号：US12099530
申请日：2008-04-08
申请人： Chang-Yu Wu , Ming-Hsin Ku , Shang-Chih Hsieh , Hsin-Shih Wang
发明人： Chang-Yu Wu , Ming-Hsin Ku , Shang-Chih Hsieh , Hsin-Shih Wang
IPC分类号： H05K1/11 , H05K1/14
CPC分类号： H01L27/0207 , H01L23/5286 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： A power supply architecture for a structural application-specific integrated circuit (ASIC) is provided. The power supply architecture includes a first conductor and a second conductor. The first conductor is coupled to a fixed voltage. The first conductor at least passes through two edges of a cell. The first conductor and the second conductor are connected through a contact. The second conductor at most passes through one edge of the cell. The structural ASIC includes a first metal layer and a second metal layer. The first metal layer includes the first conductor. The second metal layer includes the second conductor.
摘要翻译：提供了一种用于结构专用集成电路（ASIC）的电源架构。电源架构包括第一导体和第二导体。第一导体耦合到固定电压。第一导体至少穿过电池的两个边缘。第一导体和第二导体通过触点连接。第二导体最多通过电池的一个边缘。结构ASIC包括第一金属层和第二金属层。第一金属层包括第一导体。第二金属层包括第二导体。

10. 发明授权

US09142630B2 Device performance enhancement 有权
标题翻译：设备性能提升
公开(公告)号：US09142630B2
公开(公告)日：2015-09-22
申请号：US13557479
申请日：2012-07-25
申请人： Chang-Yu Wu , Chih-Chiang Chang , Shang-Chih Hsieh , Wei-Chih Hsieh
发明人： Chang-Yu Wu , Chih-Chiang Chang , Shang-Chih Hsieh , Wei-Chih Hsieh
IPC分类号： H01L21/28 , H01L29/423 , H01L29/78
CPC分类号： H01L29/4238 , H01L21/28123 , H01L29/78
摘要： Among other things, one or more techniques for enhancing device (e.g., transistor) performance are provided herein. In one embodiment, device performance is enhanced by forming an extended dummy region at an edge of a region of a device and forming an active region at a non-edge of the region. Limitations associated with semiconductor fabrication processing present in the extended dummy region more so than in non-edge regions. Accordingly, a device exhibiting enhanced performance is formed by connecting a gate to the active region, where the active region has a desired profile because it is comprised within a non-edge of the region. A dummy device (e.g., that may be less responsive) may be formed to include the extended dummy region, where the extended dummy region has a less than desired profile due to limitations associated with semiconductor fabrication processing, for example.
摘要翻译：除此之外，本文提供了用于增强器件（例如，晶体管）性能的一种或多种技术。在一个实施例中，通过在器件的区域的边缘处形成延伸的虚拟区域并在该区域的非边缘处形成有源区域来增强器件性能。与非边缘区域相比，扩展虚拟区域中存在与半导体制造处理相关的限制。因此，通过将栅极连接到有源区域来形成表现出增强的性能的器件，其中有源区域具有期望的形状，因为它包括在该区域的非边缘内。例如，由于与半导体制造处理相关的限制，可以形成虚拟设备（例如，可能较不响应的）以包括扩展的虚拟区域，其中扩展的虚拟区域具有小于期望的轮廓。

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