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1. 发明授权

US07046493B2 Input/output buffer protection circuit 有权
标题翻译：输入/输出缓冲保护电路
公开(公告)号：US07046493B2
公开(公告)日：2006-05-16
申请号：US10735324
申请日：2003-12-12
申请人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
发明人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
IPC分类号： H02H9/00
CPC分类号： H03K19/00315 , H01L27/0266
摘要： An input/output buffer protection circuit, which comprises an I/O pad, an I/O buffer, an n-well control circuit, a gate control circuit, and a protection component. The I/O buffer includes a PMOS transistor and a NMOS transistor. The n-well control circuit is coupled to an n-well of the PMOS transistor. When an input voltage higher than a source voltage is applied, voltage at the n-well of the PMOS is increased by the n-well control circuit to the input voltage level. The gate control circuit is coupled to the gate terminal of the PMOS transistor and the input/output pad. When an input voltage higher than a source voltage is applied, voltage at the gate terminal of the PMOS is increased by the gate control circuit to the source voltage level. Wherein the gate control circuit comprises a transistor and the transistor transfers a high potential control voltage to the gate of the PMOS transistor in output mode. The protection component is coupled between the gate of the transistor and the I/O pad to generate a voltage drop down path and block the I/O pad signal from flowing back to the gate of the transistor.
摘要翻译：输入/输出缓冲器保护电路，其包括I / O焊盘，I / O缓冲器，n阱控制电路，栅极控制电路和保护部件。 I / O缓冲器包括PMOS晶体管和NMOS晶体管。 n阱控制电路耦合到PMOS晶体管的n阱。当施加高于源电压的输入电压时，PMOS的n阱处的电压由n阱控制电路增加到输入电压电平。栅极控制电路耦合到PMOS晶体管的栅极端子和输入/输出焊盘。当施加高于源极电压的输入电压时，PMOS栅极端子处的电压由栅极控制电路增加到源极电压电平。其中栅极控制电路包括晶体管，并且晶体管在输出模式下将高电位控制电压传送到PMOS晶体管的栅极。保护元件耦合在晶体管的栅极和I / O焊盘之间，以产生电压降降路径，并阻止I / O焊盘信号流回晶体管的栅极。

2. 发明申请

US20050068069A1 INPUT/OUTPUT BUFFER 有权
标题翻译：输入/输出缓冲器
公开(公告)号：US20050068069A1
公开(公告)日：2005-03-31
申请号：US10673391
申请日：2003-09-30
申请人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
发明人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
IPC分类号： H03K19/003 , H03B1/00
CPC分类号： H03K19/00315
摘要： An input/output buffer. An input/output circuit has a transmission terminal coupled to an I/O pad, and a floating N-well region. A P-gate control circuit conveys the second gate control signal to the gate of the first PMOS transistor. A feedback detection device is coupled between the transmission terminal and an N-well control circuit to output a feedback signal according to an input voltage at the I/O pad. The N-well control circuit adjusts the voltage level at the N-well region of the first PMOS transistor according to the feedback signal output from the feedback detection device.
摘要翻译：一个输入/输出缓冲区。输入/输出电路具有耦合到I / O焊盘和浮动N阱区的传输端。 P栅极控制电路将第二栅极控制信号传送到第一PMOS晶体管的栅极。反馈检测装置耦合在传输终端和N阱控制电路之间，以根据I / O焊盘的输入电压输出反馈信号。 N阱控制电路根据从反馈检测装置输出的反馈信号，调整第一PMOS晶体管的N阱区域的电压电平。

3. 发明授权

US06882188B1 Input/output buffer 有权
标题翻译：输入/输出缓冲器
公开(公告)号：US06882188B1
公开(公告)日：2005-04-19
申请号：US10673391
申请日：2003-09-30
申请人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
发明人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
IPC分类号： H03K19/003 , H03B1/00
CPC分类号： H03K19/00315
摘要： An input/output buffer. An input/output circuit has a transmission terminal coupled to an I/O pad, and a floating N-well region. A P-gate control circuit conveys the second gate control signal to the gate of the first PMOS transistor. A feedback detection device is coupled between the transmission terminal and an N-well control circuit to output a feedback signal according to an input voltage at the I/O pad. The N-well control circuit adjusts the voltage level at the N-well region of the first PMOS transistor according to the feedback signal output from the feedback detection device.
摘要翻译：一个输入/输出缓冲区。输入/输出电路具有耦合到I / O焊盘和浮动N阱区的传输端。 P栅极控制电路将第二栅极控制信号传送到第一PMOS晶体管的栅极。反馈检测装置耦合在传输终端和N阱控制电路之间，以根据I / O焊盘的输入电压输出反馈信号。 N阱控制电路根据从反馈检测装置输出的反馈信号，调整第一PMOS晶体管的N阱区域的电压电平。

4. 发明授权

US06861874B1 Input/output buffer 有权
标题翻译：输入/输出缓冲器
公开(公告)号：US06861874B1
公开(公告)日：2005-03-01
申请号：US10679399
申请日：2003-10-07
申请人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
发明人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
IPC分类号： H03K19/003 , H03K19/0175
CPC分类号： H03K19/00315
摘要： An input/output buffer. An input/output circuit is composed of a first PMOS transistor and a first NMOS transistor, has an I/O port coupled to an I/O pad, and a N-well region. An N-well control circuit controls the voltage level at the N-well region of the first PMOS transistor according to input signals at the I/O pad. A P-gate control circuit receives a second gate control signal and outputs to the gate of the first PMOS transistor. The P-gate control circuit is composed of a transmission gate and a third PMOS transistor. The transmission gate and the third PMOS transistor do not have to follow the design rule for ESD, and the wafer area required for the P-gate control circuit can be decreased because the P-gate control circuit is not directly connected to the I/O pad.
摘要翻译：一个输入/输出缓冲区。输入/输出电路由第一PMOS晶体管和第一NMOS晶体管组成，具有耦合到I / O焊盘的I / O端口和N阱区域。 N阱控制电路根据I / O焊盘上的输入信号来控制第一PMOS晶体管的N阱区域的电压电平。 P栅极控制电路接收第二栅极控制信号并输出到第一PMOS晶体管的栅极。 P栅极控制电路由传输栅极和第三PMOS晶体管构成。传输栅极和第三PMOS晶体管不必遵循ESD的设计规则，因为P栅极控制电路不直接连接到I / O，所以P栅极控制电路所需的晶片面积可以减小垫。

5. 发明申请

US20050128670A1 Input/output buffer protection circuit 有权
标题翻译：输入/输出缓冲保护电路
公开(公告)号：US20050128670A1
公开(公告)日：2005-06-16
申请号：US10735324
申请日：2003-12-12
申请人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
发明人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
IPC分类号： H01L27/02 , H03K19/003 , H02H3/20
CPC分类号： H03K19/00315 , H01L27/0266
摘要： An input/output buffer protection circuit, which comprises an I/O pad, an I/O buffer, an n-well control circuit, a gate control circuit, and a protection component. The I/O buffer includes a PMOS transistor and a NMOS transistor. The n-well control circuit is coupled to an n-well of the PMOS transistor. When an input voltage higher than a source voltage is applied, voltage at the n-well of the PMOS is increased by the n-well control circuit to the input voltage level. The gate control circuit is coupled to the gate terminal of the PMOS transistor and the input/output pad. When an input voltage higher than a source voltage is applied, voltage at the gate terminal of the PMOS is increased by the gate control circuit to the source voltage level. Wherein the gate control circuit comprises a transistor and the transistor transfers a high potential control voltage to the gate of the PMOS transistor in output mode. The protection component is coupled between the gate of the transistor and the I/O pad to generate a voltage drop down path and block the I/O pad signal from flowing back to the gate of the transistor.
摘要翻译：输入/输出缓冲器保护电路，其包括I / O焊盘，I / O缓冲器，n阱控制电路，栅极控制电路和保护部件。 I / O缓冲器包括PMOS晶体管和NMOS晶体管。 n阱控制电路耦合到PMOS晶体管的n阱。当施加高于源电压的输入电压时，PMOS的n阱处的电压由n阱控制电路增加到输入电压电平。栅极控制电路耦合到PMOS晶体管的栅极端子和输入/输出焊盘。当施加高于源极电压的输入电压时，PMOS栅极端子处的电压由栅极控制电路增加到源极电压电平。其中栅极控制电路包括晶体管，并且晶体管在输出模式下将高电位控制电压传送到PMOS晶体管的栅极。保护元件耦合在晶体管的栅极和I / O焊盘之间，以产生电压降降路径，并阻止I / O焊盘信号流回晶体管的栅极。

6. 发明授权

US07764101B2 Schmitt-trigger-based level detection circuit 有权
标题翻译：基于施密特触发的电平检测电路
公开(公告)号：US07764101B2
公开(公告)日：2010-07-27
申请号：US12357965
申请日：2009-01-22
申请人： Jeng-Huang Wu , Sheng-Hua Chen
发明人： Jeng-Huang Wu , Sheng-Hua Chen
IPC分类号： H03K3/12
CPC分类号： H03K3/3565 , H03K5/082
摘要： A Schmitt trigger includes A first PMOS transistors having the drains and sources thereof serially connected and coupled between a voltage source and an output end, and having gates thereof coupled to an input end; B first NMOS transistors having the drains and sources thereof serially connected and coupled between the output end and ground, and having gates thereof coupled to the input end; C second PMOS transistors, each being coupled between ground and a node between the drain and the source of the first PMOS transistors and having the gate thereof coupled to the output end; and D second NMOS transistors, each being coupled between the voltage source and a node between the drain and the source of the first NMOS transistors and having the gate thereof coupled to the output end. A is greater than 2 and C, and B is greater than 2 and D.
摘要翻译：施密特触发器包括：第一PMOS晶体管，其漏极和源极串联连接并耦合在电压源和输出端之间，并且其栅极耦合到输入端; B第一NMOS晶体管，其漏极和源极串联连接并耦合在输出端和地之间，并且其栅极耦合到输入端; C个第二PMOS晶体管，每个PMOS晶体管分别耦合在地与第一PMOS晶体管的漏极和源极之间的节点之间，并且其栅极耦合到输出端; 和D个第二NMOS晶体管，每个都连接在电压源和第一NMOS晶体管的漏极和源极之间的节点之间，并且其栅极耦合到输出端。 A大于2，C大于2，D大于2。

7. 发明申请

US20050285689A1 Crystal oscillator circuit with activation control 失效
标题翻译：晶振电路具有启动控制功能
公开(公告)号：US20050285689A1
公开(公告)日：2005-12-29
申请号：US10876083
申请日：2004-06-24
申请人： Jeng-Huang Wu , Sheng-Hua Chen
发明人： Jeng-Huang Wu , Sheng-Hua Chen
IPC分类号： H03B1/00 , H03K3/03
CPC分类号： H03K3/0307
摘要： A CMOS Pierce crystal oscillator. A clock generator with activation control, for generating a clock signal. The clock generator comprises an amplifier, a shaping circuit and a diagnostic circuit. The amplifier is capable of being coupled to an external oscillation source through an input pad and an output pad to generate an oscillating signal, the shaping circuit is capable of being coupled to the output pad, for shaping the oscillating signal to generate a clock signal, and the diagnostic circuit is capable of being coupled to the output pad, for asserting a ready signal when amplitude of the oscillating signal exceeds a predetermined portion of a full swing voltage.
摘要翻译： CMOS皮尔斯晶体振荡器。具有启动控制的时钟发生器，用于产生时钟信号。时钟发生器包括放大器，整形电路和诊断电路。放大器能够通过输入焊盘和输出焊盘耦合到外部振荡源以产生振荡信号，整形电路能够耦合到输出焊盘，用于整形振荡信号以产生时钟信号，并且诊断电路能够耦合到输出焊盘，用于当振荡信号的振幅超过全摆幅电压的预定部分时断言就绪信号。

8. 发明申请

US20080178135A1 CELLS OF INTEGRATED CIRCUIT AND RELATED TECHNOLOGY AND METHOD 审中-公开
标题翻译：集成电路及相关技术与方法
公开(公告)号：US20080178135A1
公开(公告)日：2008-07-24
申请号：US11829870
申请日：2007-07-27
申请人： Jeng-Huang Wu , Sheng-Hua Chen , Meng-Jer Wey
发明人： Jeng-Huang Wu , Sheng-Hua Chen , Meng-Jer Wey
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Electronic cells/cell library and related technology/method capable of achieving high integration of integrated circuits. In one embodiment, the proposed technology adopts cells with cell heights equal to a non-integer multiplication of the routing track to establish a cell library, so a layout area of each cell is reduced. Further, higher integration of integrated circuit can be achieved by applying the proposed cells in integrated circuits.
摘要翻译：能够实现集成电路高集成度的电子电池/电池库及相关技术/方法。在一个实施例中，所提出的技术采用具有等于路由轨道的非整数乘法的单元高度的单元，以建立单元库，从而减小每个单元的布局面积。此外，通过在集成电路中应用所提出的单元，可以实现集成电路的更高集成度。

9. 发明授权

US07057468B2 Crystal oscillator circuit with activation control 失效
标题翻译：晶振电路具有启动控制功能
公开(公告)号：US07057468B2
公开(公告)日：2006-06-06
申请号：US10876083
申请日：2004-06-24
申请人： Jeng-Huang Wu , Sheng-Hua Chen
发明人： Jeng-Huang Wu , Sheng-Hua Chen
IPC分类号： H03B1/00 , H03L5/00 , G06F1/04
CPC分类号： H03K3/0307
摘要： A CMOS Pierce crystal oscillator. A clock generator with activation control, for generating a clock signal. The clock generator comprises an amplifier, a shaping circuit and a diagnostic circuit. The amplifier is capable of being coupled to an external oscillation source through an input pad and an output pad to generate an oscillating signal, the shaping circuit is capable of being coupled to the output pad, for shaping the oscillating signal to generate a clock signal, and the diagnostic circuit is capable of being coupled to the output pad, for asserting a ready signal when amplitude of the oscillating signal exceeds a predetermined portion of a full swing voltage.
摘要翻译： CMOS皮尔斯晶体振荡器。具有启动控制的时钟发生器，用于产生时钟信号。时钟发生器包括放大器，整形电路和诊断电路。放大器能够通过输入焊盘和输出焊盘耦合到外部振荡源以产生振荡信号，整形电路能够耦合到输出焊盘，用于整形振荡信号以产生时钟信号，并且诊断电路能够耦合到输出焊盘，用于当振荡信号的振幅超过全摆幅电压的预定部分时断言就绪信号。

10. 发明授权

US08169068B2 IO cell with multiple IO ports and related techniques for layout area saving 有权
标题翻译：具有多个IO端口的IO单元和相关技术，用于布局区域的保存
公开(公告)号：US08169068B2
公开(公告)日：2012-05-01
申请号：US12697582
申请日：2010-02-01
申请人： Jeng-Huang Wu , Hung-Yi Chang , Chun Huang
发明人： Jeng-Huang Wu , Hung-Yi Chang , Chun Huang
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/02166 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/49431 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01033 , H01L2924/01046 , H01L2924/01055 , H01L2924/01082 , H01L2924/01084 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： An IO cell with multiple IO ports and related techniques are provided. The IO cell has a plurality of IO ports for transmitting signal of a same IO pin, and each IO port corresponds to a predetermined region for containing an IO pad, wherein at least one of the plural predetermined regions of the plural IO ports partially overlaps with active circuit layout region of the IO cell. In a chip, if a given IO cell has a predetermined region of an IO port overlapping an IO pad location of another adjacent IO cell, then a predetermined region of another IO port is selected for implementing an IO pad of the given IO cell, such that the IO cells can be arranged more compactly for chip layout area saving.
摘要翻译：提供了具有多个IO端口和相关技术的IO单元。 IO单元具有用于发送相同IO引脚的信号的多个IO端口，并且每个IO端口对应于用于容纳IO垫的预定区域，其中多个IO端口的多个预定区域中的至少一个部分地与 IO单元的有源电路布局区域。在芯片中，如果给定IO单元具有与另一相邻IO单元的IO垫位置重叠的IO端口的预定区域，则选择另一IO端口的预定区域以实现给定IO单元的IO垫，可以更紧凑地布置IO单元，以节省芯片布局面积。

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