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1. 发明申请

US20090251185A1 DATA RETENTION DEVICE FOR MULTIPLE POWER DOMAINS 审中-公开
标题翻译：用于多个电源域的数据保持设备
公开(公告)号：US20090251185A1
公开(公告)日：2009-10-08
申请号：US12416380
申请日：2009-04-01
申请人： JENG-HUANG WU , CHIH-WEN YANG
发明人： JENG-HUANG WU , CHIH-WEN YANG
IPC分类号： H03K3/289
CPC分类号： H03K3/0375 , G06F1/3203 , H03K3/35625
摘要： A data retention device includes a first latch disposed between a data input terminal and a data output terminal for storing a data signal received from the data input terminal and transmitting the data signal through a data forward path to the data output terminal according to a clock signal in an operational mode; a second latch disposed in a branch of the data forward path between the first latch and the data output terminal for receiving the data signal in the operational mode and retaining the data signal in a sleep mode; and a first tri-state buffer disposed in the data forward path between the first latch and the branched second latch and enabled to conduct the data forward path in the operational mode and disabled to cut off the data forward path in the sleep mode according to a data retention signal.
摘要翻译：数据保持装置包括设置在数据输入端和数据输出端之间的第一锁存器，用于存储从数据输入端接收的数据信号，并根据时钟信号通过数据转发路径将数据信号发送到数据输出端在操作模式下设置在第一锁存器和数据输出端子之间的数据前向路径的分支中的第二锁存器，用于在操作模式下接收数据信号并将数据信号保持在睡眠模式; 以及第一三态缓冲器，其设置在第一锁存器和分支第二锁存器之间的数据前向路径中，并且能够在操作模式下传导数据前向路径，并且禁用该功能以根据睡眠模式切断数据转发路径数据保留信号。

2. 发明申请

US20090189670A1 LEVEL SHIFTER WITH REDUCED POWER CONSUMPTION AND LOW PROPAGATION DELAY 有权
标题翻译：具有降低功耗和低传播延迟的液位变送器
公开(公告)号：US20090189670A1
公开(公告)日：2009-07-30
申请号：US12357179
申请日：2009-01-21
申请人： CHIH-WEN YANG , SHENG-HUA CHEN
发明人： CHIH-WEN YANG , SHENG-HUA CHEN
IPC分类号： H03L5/00
CPC分类号： H03K19/018521
摘要： A level shifter includes a Not gate coupled to a signal input and operable between a first high level and a low level; a first PMOS transistor coupled to a second voltage source and a control end; a first NMOS transistor coupled to the first PMOS transistor, a Not-gate output end and a reference voltage; and a control circuit coupled to the signal input, the Not-gate output end and the second voltage source. When the signal input and the Not-gate output end are at the first high level and the low level, respectively, the first PMOS transistor is turned on so that the signal output is at a second high level; and when the signal input and the Not-gate output end are switched contrarily, the first PMOS transistor is turned off and the signal output is at the low level.
摘要翻译：电平移位器包括耦合到信号输入并可在第一高电平和低电平之间操作的“否”门; 耦合到第二电压源和控制端的第一PMOS晶体管; 耦合到第一PMOS晶体管的第一NMOS晶体管，非栅极输出端和参考电压; 以及耦合到信号输入，非栅极输出端和第二电压源的控制电路。当信号输入和非栅极输出端分别处于第一高电平和低电平时，第一PMOS晶体管导通，使得信号输出处于第二高电平; 并且当信号输入和非栅极输出端相反地切换时，第一PMOS晶体管被截止并且信号输出处于低电平。

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