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1. 发明授权

US09627483B2 Semiconductor devices including protruding insulation portions between active fins 有权
公开(公告)号：US09627483B2
公开(公告)日：2017-04-18
申请号：US14463394
申请日：2014-08-19
申请人： Shigenobu Maeda , Hee-Soo Kang , Sang-Pil Sim , Soo-Hun Hong
发明人： Shigenobu Maeda , Hee-Soo Kang , Sang-Pil Sim , Soo-Hun Hong
IPC分类号： H01L29/10 , H01L29/78 , H01L29/417 , H01L29/66 , B82Y10/00 , H01L27/12 , H01L29/06 , H01L27/088 , H01L21/8234 , H01L21/84 , H01L29/775
CPC分类号： H01L29/0692 , B82Y10/00 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/1037 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/41791 , H01L29/4966 , H01L29/517 , H01L29/66795 , H01L29/775 , H01L29/7848 , H01L29/785
摘要： A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.

2. 发明授权

US09419077B2 Semiconductor devices including protruding insulation portions between active fins 有权
标题翻译：半导体器件包括活性鳍片之间的突出绝缘部分
公开(公告)号：US09419077B2
公开(公告)日：2016-08-16
申请号：US14458955
申请日：2014-08-13
申请人： Shigenobu Maeda , Hee-Soo Kang , Sang-Pil Sim , Soo-Hun Hong
发明人： Shigenobu Maeda , Hee-Soo Kang , Sang-Pil Sim , Soo-Hun Hong
IPC分类号： H01L29/78 , H01L27/12 , H01L29/06 , H01L29/10 , H01L29/417 , H01L29/66 , B82Y10/00 , H01L27/088 , H01L21/8234 , H01L21/84 , H01L29/775
CPC分类号： H01L29/0692 , B82Y10/00 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/1037 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/41791 , H01L29/4966 , H01L29/517 , H01L29/66795 , H01L29/775 , H01L29/7848 , H01L29/785
摘要： A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.
摘要翻译：半导体器件可以包括场绝缘层，其包括在第一和第二正交方向上延伸的平面主表面和从主表面相对于第一和第二正交方向突出特定距离的突出部分。第一和第二多通道活性翅片可以在场绝缘层上延伸，并且可以通过突出部分彼此分离。导电层可以从突出部分的最上表面延伸到与第一和第二多通道活性鳍片之间的突出部分交叉。

3. 发明申请

US20140346602A1 SEMICONDUCTOR DEVICES INCLUDING PROTRUDING INSULATION PORTIONS BETWEEN ACTIVE FINS 审中-公开
标题翻译：半导体器件，包括有源FINS之间的推出绝缘部分
公开(公告)号：US20140346602A1
公开(公告)日：2014-11-27
申请号：US14458955
申请日：2014-08-13
申请人： Shigenobu Maeda , Hee-Soo Kang , Sang-Pil Sim , Soo-Hun Hong
发明人： Shigenobu Maeda , Hee-Soo Kang , Sang-Pil Sim , Soo-Hun Hong
IPC分类号： H01L29/78 , H01L27/12 , H01L29/06
CPC分类号： H01L29/0692 , B82Y10/00 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/1037 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/41791 , H01L29/4966 , H01L29/517 , H01L29/66795 , H01L29/775 , H01L29/7848 , H01L29/785
摘要： A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.
摘要翻译：半导体器件可以包括场绝缘层，其包括在第一和第二正交方向上延伸的平面主表面和从主表面相对于第一和第二正交方向突出特定距离的突出部分。第一和第二多通道活性翅片可以在场绝缘层上延伸，并且可以通过突出部分彼此分离。导电层可以从突出部分的最上表面延伸到与第一和第二多通道活性鳍片之间的突出部分交叉。

4. 发明申请

US20130180360A1 Method of Manufacturing Iron-Based Powder 有权
标题翻译：铁基粉末的制造方法
公开(公告)号：US20130180360A1
公开(公告)日：2013-07-18
申请号：US13824192
申请日：2011-09-15
申请人： Ha Neul Kim , Eon Sik Lee , Oh-Joon Kwon , Sun Jong Park , Hee Soo Kang
发明人： Ha Neul Kim , Eon Sik Lee , Oh-Joon Kwon , Sun Jong Park , Hee Soo Kang
IPC分类号： B22F9/08
CPC分类号： B22F9/082 , B22F2009/0828 , B22F2009/0888 , C21C5/28 , Y02P10/216
摘要： A method of manufacturing iron-based powder includes providing an iron-based molten steel manufactured through a iron making process and a steelmaking process to a tundish; and performing water atomization over the molten steel discharged through a nozzle connected to the tundish. The iron-based powder is manufactured from the molten steel refined after a molten iron tapped from a iron making process is charged into a converter without a pre-treatment process of the molten iron, thus economically providing the highly clean iron-based powder.
摘要翻译：制造铁基粉末的方法包括：通过炼铁工艺和炼钢工艺制造的铁基钢水到中间包; 并在通过与中间包连接的喷嘴排出的钢水上进行水雾化。铁水粉末由炼铁过程中的铁水从炼铁过程中抽出的铁水加入到转炉中，而不用铁水的预处理，从而经济地提供高度清洁的铁基粉末。

5. 发明授权

US08426272B2 Non-volatile memory devices including shared bit lines and methods of fabricating the same 有权
公开(公告)号：US08426272B2
公开(公告)日：2013-04-23
申请号：US13545711
申请日：2012-07-10
申请人： Young-bae Yoon , Jeong-dong Choe , Hee-soo Kang , Dong-hoon Jang , Ki-hyun Kim
发明人： Young-bae Yoon , Jeong-dong Choe , Hee-soo Kang , Dong-hoon Jang , Ki-hyun Kim
IPC分类号： H01L21/8247
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11548
摘要： Provided are non-volatile memory devices and methods of fabricating the same, including improved bit line and contact formation that may reduce resistance and parasitic capacitance, thereby reducing manufacturing costs and improving device performance. The non-volatile memory devices may include a substrate; a plurality of field regions formed on the substrate, each of the field regions including a homogeneous first field and a second field that is divided into two sub regions via a bridge region; an active region formed on the substrate and defined as having a string structure by the field regions, where at least two strings may be connected via one of the bridge regions; and a plurality of shared bit lines may be formed on the field regions and connected to the active region via bit line contacts, where the bit line contacts may be direct contacts.

6. 发明申请

US20120015512A1 METHOD OF MANUFACTURING NON-VOLATILE MEMORY DEVICE 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20120015512A1
公开(公告)日：2012-01-19
申请号：US13238084
申请日：2011-09-21
申请人： Suk-Kang SUNG , Choong-Ho Lee , Dong-Uk Choi , Hee-Soo Kang
发明人： Suk-Kang SUNG , Choong-Ho Lee , Dong-Uk Choi , Hee-Soo Kang
IPC分类号： H01L21/28
CPC分类号： H01L27/11568
摘要： A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers.
摘要翻译：非易失性存储器件包括在衬底上的场绝缘层图案，以限定衬底的有源区，场绝缘层图案的上部突出在衬底的上表面上，在有源区上的隧道绝缘层，隧道绝缘层上的电荷俘获层，电荷俘获层上的阻挡层，场绝缘层图案的上表面上的第一绝缘层，以及阻挡层和第一绝缘层上的字线结构。

7. 发明授权

US07982246B2 Selection transistor 有权
标题翻译：选择晶体管
公开(公告)号：US07982246B2
公开(公告)日：2011-07-19
申请号：US12486367
申请日：2009-06-17
申请人： Byung-kyu Cho , Hee-soo Kang , Dong-uk Choi , Choong-ho Lee
发明人： Byung-kyu Cho , Hee-soo Kang , Dong-uk Choi , Choong-ho Lee
IPC分类号： H01L29/76
CPC分类号： H01L27/11524 , H01L27/11521
摘要： Provided are a selection transistor and a method of fabricating the same. A selection transistor can be formed on an active region in a semiconductor substrate to include a gate electrode that includes recessed portions of a sidewall of the gate electrode which are recessed inward adjacent lower portions of the gate electrode to define a T-shaped cross section of the gate electrode. A tunnel insulating layer can be located between the gate electrode and the active region.
摘要翻译：提供一种选择晶体管及其制造方法。选择晶体管可以形成在半导体衬底中的有源区上，以包括栅极电极，该栅电极包括栅电极的侧壁的凹陷部分，该栅极电极的侧壁相对于栅电极的下部凹入，以限定T形截面栅电极。隧道绝缘层可以位于栅电极和有源区之间。

8. 发明申请

US20110095377A1 SEMICONDUCTOR MEMORY DEVICES 有权
标题翻译：半导体存储器件
公开(公告)号：US20110095377A1
公开(公告)日：2011-04-28
申请号：US12984860
申请日：2011-01-05
申请人： Jong-Sun Sel , Jung-Dal Choi , Choong-Ho Lee , Ju-Hyuck Chung , Hee-Soo Kang , Dong-uk Choi
发明人： Jong-Sun Sel , Jung-Dal Choi , Choong-Ho Lee , Ju-Hyuck Chung , Hee-Soo Kang , Dong-uk Choi
IPC分类号： H01L27/088
CPC分类号： H01L23/485 , H01L21/76804 , H01L21/76816 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： In some embodiments, a semiconductor memory device includes a substrate that includes a cell array region and a peripheral circuit region. The semiconductor memory device further includes a device isolation pattern on the substrate. The device isolation pattern defines a first active region and a second active region within the cell array region and a third active region in the peripheral circuit region. The semiconductor memory device further includes a first common source region, a plurality of first source/drain regions, and a first drain region in the first active region. The semiconductor memory device further includes a second common source region, a plurality of second source/drain regions, and a second drain region in the second active region. The semiconductor memory device further includes a third source/drain region in the third active region. The semiconductor memory device further includes a common source line contacting the first and second common source regions.
摘要翻译：在一些实施例中，半导体存储器件包括包括单元阵列区域和外围电路区域的衬底。半导体存储器件还包括在衬底上的器件隔离图案。器件隔离图案限定了单元阵列区域内的第一有源区和第二有源区以及外围电路区中的第三有源区。半导体存储器件还包括第一有源区中的第一公共源极区，多个第一源极/漏极区和第一漏极区。半导体存储器件还包括第二公共源极区域，多个第二源极/漏极区域和第二有源区域中的第二漏极区域。半导体存储器件还包括第三有源区中的第三源/漏区。半导体存储器件还包括与第一和第二公共源极区域接触的公共源极线。

9. 发明授权

US07834391B2 Integrated circuit memory devices including memory cells on adjacent pedestals having different heights, and methods of fabricating same 有权
标题翻译：包括具有不同高度的相邻基座上的存储单元的集成电路存储器件及其制造方法
公开(公告)号：US07834391B2
公开(公告)日：2010-11-16
申请号：US12107918
申请日：2008-04-23
申请人： Hee-Soo Kang , Choong-Ho Lee
发明人： Hee-Soo Kang , Choong-Ho Lee
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11568
摘要： Coupling among adjacent rows of memory cells on an integrated circuit substrate may reduced by forming the adjacent rows of memory cells on adjacent semiconductor pedestals that extend different distances away from the integrated circuit substrate. NAND flash memory devices that include different pedestal heights and fabrication methods for integrated circuit memory devices are also disclosed.
摘要翻译：在集成电路基板上的相邻行存储单元之间的耦合可通过在距离集成电路基板延伸不同距离的相邻半导体基座上形成相邻行的存储单元来减小。还公开了包括不同基座高度的NAND闪存器件和用于集成电路存储器件的制造方法。

10. 发明授权

US07804137B2 Field effect transistor (FET) devices and methods of manufacturing FET devices 有权
标题翻译：场效应晶体管（FET）器件和制造FET器件的方法
公开(公告)号：US07804137B2
公开(公告)日：2010-09-28
申请号：US11930265
申请日：2007-10-31
申请人： Hee-soo Kang , Dong-gun Park , Choong-ho Lee , Hye-Jin Cho , Young-Joon Ahn
发明人： Hee-soo Kang , Dong-gun Park , Choong-ho Lee , Hye-Jin Cho , Young-Joon Ahn
IPC分类号： H01L23/62
CPC分类号： H01L29/785 , H01L21/8221 , H01L21/823437 , H01L21/823456 , H01L21/84 , H01L27/0688 , H01L27/105 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/4908 , H01L29/66787 , H01L29/66795 , H01L2924/0002 , H01L2924/00
摘要： In one aspect, a semiconductor substrate is provided having a cell area and a peripheral circuit area, and a mask layer is formed over the cell area and the peripheral circuit area of the semiconductor substrate. A FinFET gate is fabricated by forming a first opening in the mask layer to expose a first gate region in the cell area of the semiconductor substrate, and then forming a FinFET gate electrode in the first opening using a damascene process. A MOSFET gate fabricated by forming a second opening in the mask layer to expose a second gate region in the peripheral circuit area of the semiconductor substrate, and then forming a MOSFET gate electrode in the second opening using a damascene process.
摘要翻译：一方面，提供具有单元区域和外围电路区域的半导体基板，并且在半导体基板的单元区域和外围电路区域上形成掩模层。通过在掩模层中形成第一开口以暴露半导体衬底的单元区域中的第一栅极区域，然后使用镶嵌工艺在第一开口中形成FinFET栅电极来制造FinFET栅极。通过在掩模层中形成第二开口以暴露半导体衬底的外围电路区域中的第二栅极区域，然后使用镶嵌工艺在第二开口中形成MOSFET栅电极来制造MOSFET栅极。

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