专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120015512A1 METHOD OF MANUFACTURING NON-VOLATILE MEMORY DEVICE 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20120015512A1
公开(公告)日：2012-01-19
申请号：US13238084
申请日：2011-09-21
申请人： Suk-Kang SUNG , Choong-Ho Lee , Dong-Uk Choi , Hee-Soo Kang
发明人： Suk-Kang SUNG , Choong-Ho Lee , Dong-Uk Choi , Hee-Soo Kang
IPC分类号： H01L21/28
CPC分类号： H01L27/11568
摘要： A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers.
摘要翻译：非易失性存储器件包括在衬底上的场绝缘层图案，以限定衬底的有源区，场绝缘层图案的上部突出在衬底的上表面上，在有源区上的隧道绝缘层，隧道绝缘层上的电荷俘获层，电荷俘获层上的阻挡层，场绝缘层图案的上表面上的第一绝缘层，以及阻挡层和第一绝缘层上的字线结构。

2. 发明授权

US08455344B2 Method of manufacturing non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US08455344B2
公开(公告)日：2013-06-04
申请号：US13238084
申请日：2011-09-21
申请人： Suk-Kang Sung , Choong-Ho Lee , Dong-Uk Choi , Hee-Soo Kang
发明人： Suk-Kang Sung , Choong-Ho Lee , Dong-Uk Choi , Hee-Soo Kang
IPC分类号： H01L21/28
CPC分类号： H01L27/11568
摘要： A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers.
摘要翻译：非易失性存储器件包括在衬底上的场绝缘层图案，以限定衬底的有源区，场绝缘层图案的上部突出在衬底的上表面上，在有源区上的隧道绝缘层，隧道绝缘层上的电荷俘获层，电荷俘获层上的阻挡层，场绝缘层图案的上表面上的第一绝缘层，以及阻挡层和第一绝缘层上的字线结构。

3. 发明授权

US08120091B2 Non-volatile memory devices including a floating gate and methods of manufacturing the same 有权
标题翻译：包括浮动栅极的非易失性存储器件及其制造方法
公开(公告)号：US08120091B2
公开(公告)日：2012-02-21
申请号：US12128078
申请日：2008-05-28
申请人： Suk-Kang Sung , Choong-Ho Lee , Sang-wook Lim , Dong-Uk Choi , Hee-Soo Kang , Kyu-Charn Park
发明人： Suk-Kang Sung , Choong-Ho Lee , Sang-wook Lim , Dong-Uk Choi , Hee-Soo Kang , Kyu-Charn Park
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A non-volatile memory device includes a substrate and a tunnel insulation layer pattern, such that each portion of the tunnel insulation pattern extends along a first direction and adjacent portions of the tunnel insulation layer pattern may be separated in a second direction that is substantially perpendicular to the first direction. A non-volatile memory device may include a gate structure formed on the tunnel insulation layer pattern. The gate structure may include a floating gate formed on the tunnel insulation layer pattern along the second direction, a first conductive layer pattern formed on the floating gate in the second direction, a dielectric layer pattern formed on the first conductive layer pattern along the second direction, and a control gate formed on the dielectric layer pattern in the second direction.
摘要翻译：非易失性存储器件包括衬底和隧道绝缘层图案，使得隧道绝缘图案的每个部分沿着第一方向延伸，并且隧道绝缘层图案的相邻部分可以在基本垂直的第二方向上分离到第一个方向。非易失性存储器件可以包括形成在隧道绝缘层图案上的栅极结构。栅极结构可以包括沿着第二方向形成在隧道绝缘层图案上的浮动栅极，在第二方向上形成在浮置栅极上的第一导电层图案，沿着第二方向形成在第一导电层图案上的电介质层图案以及在第二方向上形成在电介质层图案上的控制栅极。

4. 发明授权

US08044453B2 Non-volatile memory device with a charge trapping layer 有权
标题翻译：具有电荷捕获层的非易失性存储器件
公开(公告)号：US08044453B2
公开(公告)日：2011-10-25
申请号：US12318451
申请日：2008-12-30
申请人： Suk-Kang Sung , Choong-Ho Lee , Dong-Uk Choi , Hee-Soo Kang
发明人： Suk-Kang Sung , Choong-Ho Lee , Dong-Uk Choi , Hee-Soo Kang
IPC分类号： H01L29/792
CPC分类号： H01L27/11568
摘要： A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers.
摘要翻译：非易失性存储器件包括在衬底上的场绝缘层图案，以限定衬底的有源区，场绝缘层图案的上部突出在衬底的上表面上，在有源区上的隧道绝缘层，隧道绝缘层上的电荷俘获层，电荷俘获层上的阻挡层，场绝缘层图案的上表面上的第一绝缘层，以及阻挡层和第一绝缘层上的字线结构。

5. 发明申请

US20090166714A1 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US20090166714A1
公开(公告)日：2009-07-02
申请号：US12318451
申请日：2008-12-30
申请人： Suk-Kang Sung , Choong-Ho Lee , Dong-Uk Choi , Hee-Soo Kang
发明人： Suk-Kang Sung , Choong-Ho Lee , Dong-Uk Choi , Hee-Soo Kang
IPC分类号： H01L29/792
CPC分类号： H01L27/11568
摘要： A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers.
摘要翻译：非易失性存储器件包括在衬底上的场绝缘层图案，以限定衬底的有源区，场绝缘层图案的上部突出在衬底的上表面上，在有源区上的隧道绝缘层，隧道绝缘层上的电荷俘获层，电荷俘获层上的阻挡层，场绝缘层图案的上表面上的第一绝缘层，以及阻挡层和第一绝缘层上的字线结构。

6. 发明申请

US20080296657A1 Non-Volatile Memory Devices and Methods of Manufacturing Non-Volatile Memory Devices 有权
标题翻译：非易失性存储器件和制造非易失性存储器件的方法
公开(公告)号：US20080296657A1
公开(公告)日：2008-12-04
申请号：US12128078
申请日：2008-05-28
申请人： Suk-Kang Sung , Choong-Ho Lee , Sang-wook Lim , Dong-Uk Choi , Hee-Soo Kang , Kyu-Charn Park
发明人： Suk-Kang Sung , Choong-Ho Lee , Sang-wook Lim , Dong-Uk Choi , Hee-Soo Kang , Kyu-Charn Park
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A non-volatile memory device includes a substrate and a tunnel insulation layer pattern, such that each portion of the tunnel insulation pattern extends along a first direction and adjacent portions of the tunnel insulation layer pattern may be separated in a second direction that is substantially perpendicular to the first direction. A non-volatile memory device may include a gate structure formed on the tunnel insulation layer pattern. The gate structure may include a floating gate formed on the tunnel insulation layer pattern along the second direction, a first conductive layer pattern formed on the floating gate in the second direction, a dielectric layer pattern formed on the first conductive layer pattern along the second direction, and a control gate formed on the dielectric layer pattern in the second direction.
摘要翻译：非易失性存储器件包括衬底和隧道绝缘层图案，使得隧道绝缘图案的每个部分沿着第一方向延伸，并且隧道绝缘层图案的相邻部分可以在基本垂直的第二方向上分离到第一个方向。非易失性存储器件可以包括形成在隧道绝缘层图案上的栅极结构。栅极结构可以包括沿着第二方向形成在隧道绝缘层图案上的浮动栅极，在第二方向上形成在浮置栅极上的第一导电层图案，沿着第二方向形成在第一导电层图案上的电介质层图案以及在第二方向上形成在电介质层图案上的控制栅极。

7. 发明授权

US07867849B2 Method of manufacturing a non-volatile semiconductor device 有权
标题翻译：制造非易失性半导体器件的方法
公开(公告)号：US07867849B2
公开(公告)日：2011-01-11
申请号：US12222074
申请日：2008-08-01
申请人： Choong-Ho Lee , Jai-Hyuk Song , Dong-Uk Choi , Suk-Kang Sung
发明人： Choong-Ho Lee , Jai-Hyuk Song , Dong-Uk Choi , Suk-Kang Sung
IPC分类号： H01L21/336
CPC分类号： H01L21/324 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Example embodiments relate to methods of fabricating a non-volatile memory device. According to example embodiments, a method of fabricating a non-volatile memory device may include forming at least one gate structure on an upper face of a substrate. The at least one gate structure may include a tunnel insulation layer pattern, a charge storing layer pattern, a dielectric layer pattern and a control gate. According to example embodiments, a method of fabricating a non-volatile memory device may also include forming a silicon nitride layer on the upper face of the substrate to cover the at least one gate structure, forming an insulating interlayer on the silicon nitride layer on the upper face of the substrate, and providing an annealing gas toward the upper face of the substrate and a lower face of the substrate to cure defects of the tunnel insulation layer pattern.
摘要翻译：示例实施例涉及制造非易失性存储器件的方法。根据示例性实施例，制造非易失性存储器件的方法可以包括在衬底的上表面上形成至少一个栅极结构。至少一个栅极结构可以包括隧道绝缘层图案，电荷存储层图案，电介质层图案和控制栅极。根据示例实施例，制造非易失性存储器件的方法还可以包括在衬底的上表面上形成氮化硅层以覆盖至少一个栅极结构，在氮化硅层上形成绝缘中间层并且朝向基板的上表面和基板的下表面提供退火气体，以固化隧道绝缘层图案的缺陷。

8. 发明申请

US20090035906A1 Method of manufacturing a non-volatile semiconductor device 有权
标题翻译：制造非易失性半导体器件的方法
公开(公告)号：US20090035906A1
公开(公告)日：2009-02-05
申请号：US12222074
申请日：2008-08-01
申请人： Choong-Ho Lee , Jai-Hyuk Song , Dong-Uk Choi , Suk-Kang Sung
发明人： Choong-Ho Lee , Jai-Hyuk Song , Dong-Uk Choi , Suk-Kang Sung
IPC分类号： H01L21/336
CPC分类号： H01L21/324 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Example embodiments relate to methods of fabricating a non-volatile memory device. According to example embodiments, a method of fabricating a non-volatile memory device may include forming at least one gate structure on an upper face of a substrate. The at least one gate structure may include a tunnel insulation layer pattern, a charge storing layer pattern, a dielectric layer pattern and a control gate. According to example embodiments, a method of fabricating a non-volatile memory device may also include forming a silicon nitride layer on the upper face of the substrate to cover the at least one gate structure, forming an insulating interlayer on the silicon nitride layer on the upper face of the substrate, and providing an annealing gas toward the upper face of the substrate and a lower face of the substrate to cure defects of the tunnel insulation layer pattern.
摘要翻译：示例实施例涉及制造非易失性存储器件的方法。根据示例性实施例，制造非易失性存储器件的方法可以包括在衬底的上表面上形成至少一个栅极结构。至少一个栅极结构可以包括隧道绝缘层图案，电荷存储层图案，电介质层图案和控制栅极。根据示例实施例，制造非易失性存储器件的方法还可以包括在衬底的上表面上形成氮化硅层以覆盖至少一个栅极结构，在氮化硅层上形成绝缘中间层并且朝向基板的上表面和基板的下表面提供退火气体，以固化隧道绝缘层图案的缺陷。

9. 发明申请

US20110095377A1 SEMICONDUCTOR MEMORY DEVICES 有权
标题翻译：半导体存储器件
公开(公告)号：US20110095377A1
公开(公告)日：2011-04-28
申请号：US12984860
申请日：2011-01-05
申请人： Jong-Sun Sel , Jung-Dal Choi , Choong-Ho Lee , Ju-Hyuck Chung , Hee-Soo Kang , Dong-uk Choi
发明人： Jong-Sun Sel , Jung-Dal Choi , Choong-Ho Lee , Ju-Hyuck Chung , Hee-Soo Kang , Dong-uk Choi
IPC分类号： H01L27/088
CPC分类号： H01L23/485 , H01L21/76804 , H01L21/76816 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： In some embodiments, a semiconductor memory device includes a substrate that includes a cell array region and a peripheral circuit region. The semiconductor memory device further includes a device isolation pattern on the substrate. The device isolation pattern defines a first active region and a second active region within the cell array region and a third active region in the peripheral circuit region. The semiconductor memory device further includes a first common source region, a plurality of first source/drain regions, and a first drain region in the first active region. The semiconductor memory device further includes a second common source region, a plurality of second source/drain regions, and a second drain region in the second active region. The semiconductor memory device further includes a third source/drain region in the third active region. The semiconductor memory device further includes a common source line contacting the first and second common source regions.
摘要翻译：在一些实施例中，半导体存储器件包括包括单元阵列区域和外围电路区域的衬底。半导体存储器件还包括在衬底上的器件隔离图案。器件隔离图案限定了单元阵列区域内的第一有源区和第二有源区以及外围电路区中的第三有源区。半导体存储器件还包括第一有源区中的第一公共源极区，多个第一源极/漏极区和第一漏极区。半导体存储器件还包括第二公共源极区域，多个第二源极/漏极区域和第二有源区域中的第二漏极区域。半导体存储器件还包括第三有源区中的第三源/漏区。半导体存储器件还包括与第一和第二公共源极区域接触的公共源极线。

10. 发明申请

US20090190398A1 Method of programming data in a NAND flash memory device and method of reading data in the NAND flash memory device 有权
标题翻译：在NAND闪存器件中对数据进行编程的方法以及在NAND闪存器件中读取数据的方法
公开(公告)号：US20090190398A1
公开(公告)日：2009-07-30
申请号：US12289847
申请日：2008-11-05
申请人： Hee-Soo Kang , Choong-Ho Lee , Dong-Uk Choi
发明人： Hee-Soo Kang , Choong-Ho Lee , Dong-Uk Choi
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C2211/5641
摘要： A method of programming data in a NAND flash memory device including at least one even bitline and at least one odd bitline, the method including programming N-bit data into first cells coupled to the at least one even bitline or the at least one odd bitline and programming M-bit data into second cells coupled to the other of the at least one even bitline and the at least one odd bitline, where N is a natural number greater than one and M is a natural number greater than N.
摘要翻译：一种在包括至少一个偶数位线和至少一个奇数位线的NAND闪存器件中编程数据的方法，所述方法包括将N位数据编程到耦合到所述至少一个偶数位线或所述至少一个奇数位线以及将M位数据编程到耦合到所述至少一个偶数位线和所述至少一个奇数位线中的另一个的第二单元中，其中N是大于1的自然数，M是大于N的自然数。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式