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1. 发明申请

US20140159158A1 Semiconductor Devices 审中-公开
标题翻译：半导体器件
公开(公告)号：US20140159158A1
公开(公告)日：2014-06-12
申请号：US14100054
申请日：2013-12-09
申请人： Ho-Jun Kim , Chulhong Park , Jung-Ho Do , Sang-Pil Sim , Jongshik Yoon , Kwanyoung Chun
发明人： Ho-Jun Kim , Chulhong Park , Jung-Ho Do , Sang-Pil Sim , Jongshik Yoon , Kwanyoung Chun
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L21/76895 , H01L21/823475 , H01L23/485 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes transistors provided on a substrate and including first dopant regions, first contacts extending from the first dopant regions in a first direction, a long via provided on the first contacts and connected in common to first contacts that are adjacent one another, and a common conductive line provided on the long via and extending in a second direction crossing the first direction. The common conductive line electrically connects the first dopant regions to each other.
摘要翻译：半导体器件包括设置在衬底上并包括第一掺杂区的晶体管，从第一方向从第一掺杂区延伸的第一触点，设置在第一触点上的长通路，并且被共同连接到彼此相邻的第一触点，以及设置在长通孔上并沿与第一方向交叉的第二方向延伸的公共导线。公共导线将第一掺杂区彼此电连接。

2. 发明授权

US07397704B2 Flash memory device and program method thereof 失效
标题翻译：闪存装置及其编程方法
公开(公告)号：US07397704B2
公开(公告)日：2008-07-08
申请号：US11616322
申请日：2006-12-27
申请人： Sang-Pil Sim
发明人： Sang-Pil Sim
IPC分类号： G11C16/00
CPC分类号： G11C16/3404 , G11C16/3454 , G11C16/3459
摘要： A method of programming a plurality of memory cells in a flash memory device from a first state to a second state includes verifying the plurality of memory cells using a verify voltage having a level increased according to an increase in a program loop number; and programming the plurality of memory cells using a program voltage having an increment decreased according to an increase in the program loop number, wherein the verifying and programming steps constitute a program loop, the program loop being terminated at a point in time when a level of the verify voltage reaches to a voltage range of the second state.
摘要翻译：将闪速存储装置中的多个存储单元从第一状态编程到第二状态的方法包括使用根据程序循环数的增加具有增加的级别的验证电压来验证多个存储单元; 以及使用具有根据所述程序循环编号的增加而减小的增量的程序电压对所述多个存储单元进行编程，其中所述验证和编程步骤构成程序循环，所述程序循环在等级验证电压达到第二状态的电压范围。

3. 发明授权

US07271436B2 Flash memory devices including a pass transistor 有权
标题翻译：包括传输晶体管的闪存器件
公开(公告)号：US07271436B2
公开(公告)日：2007-09-18
申请号：US11021232
申请日：2004-12-23
申请人： Chang-Hyun Lee , Sang-Pil Sim , Seung-Keun Lee
发明人： Chang-Hyun Lee , Sang-Pil Sim , Seung-Keun Lee
IPC分类号： H01L29/76 , H01L29/788 , H01L29/94 , H01L31/00
CPC分类号： H01L27/11546 , H01L27/105 , H01L27/11526 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： Flash memory integrated circuit devices include an integrated circuit substrate. A cell array on the integrated circuit substrate includes a plurality of cell transistors. A bit line is coupled to ones of the plurality of cell transistors and a first pass transistor is coupled to the bit line. The first pass transistor has a first diffusion structure configured to provide a breakdown voltage higher than that of a second diffusion structure. One or more second pass transistor(s) are coupled to the first pass transistor. The second pass transistor(s) have the second diffusion structure. The second diffusion structure may have a resistance smaller than a resistance of the first diffusion structure.
摘要翻译：闪存集成电路器件包括集成电路基板。集成电路基板上的单元阵列包括多个单元晶体管。位线耦合到多个单元晶体管中的一个，并且第一传输晶体管耦合到位线。第一传输晶体管具有第一扩散结构，其被配置为提供比第二扩散结构高的击穿电压。一个或多个第二传输晶体管耦合到第一传输晶体管。第二传输晶体管具有第二扩散结构。第二扩散结构可以具有小于第一扩散结构的电阻的电阻。

4. 发明授权

US06399476B2 Multilayer passivation process for forming air gaps within a dielectric between interconnections 有权
标题翻译：用于在互连之间的电介质内形成气隙的多层钝化工艺
公开(公告)号：US06399476B2
公开(公告)日：2002-06-04
申请号：US09432101
申请日：1999-11-02
申请人： Jin Yang Kim , Si-Woo Lee , Won Seong Lee , Sang-Pil Sim
发明人： Jin Yang Kim , Si-Woo Lee , Won Seong Lee , Sang-Pil Sim
IPC分类号： H01C214763
CPC分类号： H01L21/7682
摘要： A process for forming air gaps within an interlayer dielectric is provided to reduce loading capacitance between interconnections. A first dielectric layer is deposited on the spaced interconnections. This first dielectric layer is deposited more thickly at the top sides than at the bottom sides of the interconnections. A second dielectric layer is deposited on the first dielectric layer to a controlled thickness that causes formation of air gaps therewithin between the interconnections. The poor step coverage of the first dielectric layer makes it easier to form the air gaps. Air gaps between interconnections allows reduced permittivity of the overall dielectric structures and thereby reduces the interconnect line to line capacitance, and increases the possible operation speed of the semiconductor device.
摘要翻译：提供了一种用于在层间电介质内形成气隙的工艺，以减少互连之间的负载电容。第一介电层沉积在间隔开的互连上。该第一电介质层在顶侧比在互连的底侧更厚地沉积。第二电介质层沉积在第一介电层上至受控的厚度，导致在互连之间形成空隙。第一电介质层的差的台阶覆盖使得容易形成气隙。互连之间的空气间隙允许整个电介质结构的介电常数降低，从而将互连线减少到线路电容，并且增加半导体器件的可能的操作速度。

5. 发明授权

US6097078A Method for forming triple well in semiconductor device 有权
标题翻译：在半导体器件中形成三阱的方法
公开(公告)号：US6097078A
公开(公告)日：2000-08-01
申请号：US275908
申请日：1999-03-24
申请人： Sang-pil Sim , Won-saong Lee
发明人： Sang-pil Sim , Won-saong Lee
IPC分类号： H01L21/8242 , H01L27/092 , H01L27/02 , H01L21/8238
CPC分类号： H01L27/10894 , H01L27/0928
摘要： A method is provided for forming a triple well of a semiconductor memory device, where a second well of a second conductive type encloses a second well of a first conductive type. A single mask is used for ion implanting the base of the enclosing well and also the entire enclosed well, which inherently avoids misalignment. Additional doping is provided to the location where the sidewalls of the enclosing well join its base. This is accomplished either by a second, deeper ion implant of the sidewalls, or by ion implanting the base at an angle and rotating it, or both. Alternately, the single mask pattern is processed between the ion implantation steps to alter its width.
摘要翻译：提供了一种用于形成半导体存储器件的三阱的方法，其中第二导电类型的第二阱包围第一导电类型的第二阱。单个掩模用于离子注入封闭井的底部以及整个封闭的井，这固有地避免了未对准。另外的掺杂被提供到封闭井的侧壁连接其底部的位置。这可以通过侧壁的第二更深的离子注入，或通过以一定角度离子注入基底并使其旋转或两者来实现。或者，在离子注入步骤之间处理单个掩模图案以改变其宽度。

6. 发明授权

US5399518A Method for manufacturing a multiple walled capacitor of a semiconductor device 失效
标题翻译：制造半导体器件的多层电容器的方法
公开(公告)号：US5399518A
公开(公告)日：1995-03-21
申请号：US91369
申请日：1993-07-15
申请人： Sang-pil Sim , Joo-young Yun , Chang-kyu Hwang , Jeong-gil Lee , Chul-ho Shin , Won-woo Lee
发明人： Sang-pil Sim , Joo-young Yun , Chang-kyu Hwang , Jeong-gil Lee , Chul-ho Shin , Won-woo Lee
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91 , H01L28/92
摘要： A method for manufacturing a double-cylindrical storage electrode of a capacitor of a semiconductor memory device, utilizes an outer etching mask for forming an outer cylinder and an inner etching mask for forming an inner cylinder. After forming a conductive structure on a semiconductor substrate, an outer etching mask for forming an outer cylinder and an inner etching mask for forming an inner cylinder are formed on the conductive structure. Then, the conductive structure is anisotropically etched using the outer and inner etching masks, thereby forming a double-cylindrical first electrode. Since a double-cylindrical storage electrode can be obtained from a single conductive layer, the influence of native oxidation circumvented. In addition, the double-cylindrical storage electrode of the capacitor according to the present invention decreases the risk of structural fragmenting because the electrode is obtained from one material layer, instead of a combination of layers as is conventionally-known. Also, the storage electrode of the present invention has no sharp edges, so that leakage current can be minimized or avoided.
摘要翻译：一种用于制造半导体存储器件的电容器的双圆柱形存储电极的方法，利用用于形成外圆筒的外蚀刻掩模和用于形成内筒的内蚀刻掩模。在半导体衬底上形成导电结构之后，在导电结构上形成用于形成外筒的外蚀刻掩模和用于形成内筒的内蚀刻掩模。然后，使用外蚀刻掩模和内蚀刻掩模对导电结构进行各向异性蚀刻，从而形成双圆柱形第一电极。由于可以从单个导电层获得双圆柱形存储电极，因此避免了天然氧化的影响。此外，根据本发明的电容器的双圆柱形存储电极降低了结构碎裂的风险，因为电极是从一个材料层获得的，而不是如传统已知的层的组合。此外，本发明的存储电极没有尖锐的边缘，使得可以最小化或避免泄漏电流。

7. 发明申请

US20140353769A1 SEMICONDUCTOR DEVICES INCLUDING PROTRUDING INSULATION PORTIONS BETWEEN ACTIVE FINS 审中-公开
公开(公告)号：US20140353769A1
公开(公告)日：2014-12-04
申请号：US14463394
申请日：2014-08-19
申请人： Shigenobu Maeda , Hee-Soo Kang , Sang-Pil Sim , Soo-Hun Hong
发明人： Shigenobu Maeda , Hee-Soo Kang , Sang-Pil Sim , Soo-Hun Hong
IPC分类号： H01L29/10 , H01L27/088 , H01L29/78
CPC分类号： H01L29/0692 , B82Y10/00 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/1037 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/41791 , H01L29/4966 , H01L29/517 , H01L29/66795 , H01L29/775 , H01L29/7848 , H01L29/785
摘要： A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.

8. 发明申请

US20070105309A1 Contactless nonvolatile memory device and method of forming the same 有权
公开(公告)号：US20070105309A1
公开(公告)日：2007-05-10
申请号：US11590620
申请日：2006-10-31
申请人： Wook-Hyun Kwon , Chan-Kwang Park , Sang-Pil Sim
发明人： Wook-Hyun Kwon , Chan-Kwang Park , Sang-Pil Sim
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of forming a contactless nonvolatile memory device includes preparing a semiconductor substrate including a cell array region, forming a plurality of mask patterns being parallel to each other on the semiconductor substrate in the cell array region, etching the semiconductor substrate using the mask patterns as an etch mask to form a plurality of recess regions, forming a gate insulating layer on sidewalls and bottoms of the recess regions, forming a floating gate layer on an upper surface of the semiconductor substrate to fill the recess regions, planarizing the floating gate layer to expose upper surfaces of the mask patterns and to form floating gate patterns in the recess regions, forming buried impurity diffusion regions in the semiconductor substrate under the mask patterns, forming an intergate dielectric layer, forming a control gate layer, and patterning the control gate layer, the intergate dielectric layer and the floating gate pattern to form a plurality of parallel word lines crossing the mask patterns, floating gates between the word lines and the recess regions, and an intergate dielectric pattern between the floating gates and the word lines, and to expose the recess regions and the mask patterns between word lines.

9. 发明授权

US07075142B2 Cell arrays of memory devices having extended source strapping regions 失效
标题翻译：具有扩展源束带区域的存储器件的单元阵列
公开(公告)号：US07075142B2
公开(公告)日：2006-07-11
申请号：US10988785
申请日：2004-11-15
申请人： Sang-pil Sim , Chan-kwang Park
发明人： Sang-pil Sim , Chan-kwang Park
IPC分类号： H01L29/788
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/115
摘要： A cell array of a flash memory device includes extended source strapping regions. The cell array includes a device isolation layer and active regions. The device isolation layer is formed in a semiconductor substrate, and the active regions are defined by the device isolation layer. Word lines cross over the active regions, and a common source line electrically connects the active regions between two word lines of word line pairs. A source strapping region is defined between the two word lines of the word line pairs. The source strapping region crosses multiple active regions.
摘要翻译：快闪存储器件的单元阵列包括扩展的源束带区域。电池阵列包括器件隔离层和有源区。器件隔离层形成在半导体衬底中，有源区由器件隔离层限定。字线跨越有源区，并且公共源极线电连接字线对的两个字线之间的有源区。在字线对的两个字线之间定义源带束带区域。源束带区域穿过多个活动区域。

10. 发明申请

US20060030102A1 Flash memory devices including a pass transistor and methods of forming the same 有权
标题翻译：包括传输晶体管的闪存器件及其形成方法
公开(公告)号：US20060030102A1
公开(公告)日：2006-02-09
申请号：US11021232
申请日：2004-12-23
申请人： Chang-Hyun Lee , Sang-Pil Sim , Seung-Keun Lee
发明人： Chang-Hyun Lee , Sang-Pil Sim , Seung-Keun Lee
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L27/11546 , H01L27/105 , H01L27/11526 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： Flash memory integrated circuit devices include an integrated circuit substrate. A cell array on the integrated circuit substrate includes a plurality of cell transistors. A bit line is coupled to ones of the plurality of cell transistors and a first pass transistor is coupled to the bit line. The first pass transistor has a first diffusion structure configured to provide a breakdown voltage higher than that of a second diffusion structure. One or more second pass transistor(s) are coupled to the first pass transistor. The second pass transistor(s) have the second diffusion structure. The second diffusion structure may have a resistance smaller than a resistance of the first diffusion structure.
摘要翻译：闪存集成电路器件包括集成电路基板。集成电路基板上的单元阵列包括多个单元晶体管。位线耦合到多个单元晶体管中的一个，并且第一传输晶体管耦合到位线。第一传输晶体管具有第一扩散结构，其被配置为提供比第二扩散结构高的击穿电压。一个或多个第二传输晶体管耦合到第一传输晶体管。第二传输晶体管具有第二扩散结构。第二扩散结构可以具有小于第一扩散结构的电阻的电阻。

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