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1. 发明授权

US08466511B2 Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same 有权
标题翻译：具有增加的源/漏接触面积的垂直沟道鳍场效应晶体管及其制造方法
公开(公告)号：US08466511B2
公开(公告)日：2013-06-18
申请号：US12613025
申请日：2009-11-05
申请人： Chang-Woo Oh , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Dong-Won Kim
发明人： Chang-Woo Oh , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Dong-Won Kim
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/78618
摘要： A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts are formed on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode. The channel region may be narrower than the first and second source/drain regions of the fin-shaped active region.
摘要翻译：翅片场效应晶体管（FinFET）器件包括其中具有第一和第二源极/漏极区域的鳍状有源区域以及从半导体衬底垂直突出的沟道区域。栅电极形成在沟道区的上表面和侧壁上。第一和第二源极/漏极触点形成在栅极电极的相对侧的鳍状有源区域的第一和第二源极/漏极区域的相应上表面和侧壁上。沟道区域可以比鳍状有源区域的第一和第二源极/漏极区域窄。

2. 发明授权

US07902024B2 Nonvolatile semiconductor device including a floating gate, method of manufacturing the same and associated systems 失效
标题翻译：包括浮动栅极的非易失性半导体器件，其制造方法和相关系统
公开(公告)号：US07902024B2
公开(公告)日：2011-03-08
申请号：US11896982
申请日：2007-09-07
申请人： Se-Hoon Lee , Donghoon Jang , Jong Jin Lee , Jeong-Dong Choe
发明人： Se-Hoon Lee , Donghoon Jang , Jong Jin Lee , Jeong-Dong Choe
IPC分类号： H01L21/336
CPC分类号： H01L29/42324 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.
摘要翻译：存储器件包括在衬底中相邻隔离层之间的衬底上的第一浮置栅电极，第一浮置栅极的至少一部分突出在相邻隔离层的一部分上方，第二浮栅电极电连接到第一浮栅浮栅电极，在至少一个相邻的隔离层上，第一和第二浮置栅电极之上的电介质层，以及介电层上的控制栅极以及第一和第二浮栅电极。

3. 发明申请

US20100173469A1 METHODS OF MANUFACTURING CHARGE TRAP-TYPE NON-VOLATILE MEMORY DEVICES 有权
标题翻译：制造电荷陷波型非易失性存储器件的方法
公开(公告)号：US20100173469A1
公开(公告)日：2010-07-08
申请号：US12651781
申请日：2010-01-04
申请人： Hak-Sun Lee , Kyoung-Sub Shin , Jeong-Dong Choe
发明人： Hak-Sun Lee , Kyoung-Sub Shin , Jeong-Dong Choe
IPC分类号： H01L21/76
CPC分类号： H01L27/11568
摘要： Some methods are directed to manufacturing charge trap-type non-volatile memory devices. An isolation layer pattern can be formed that extends in a first direction in a substrate. A recess unit is formed in the substrate by recessing an exposed surface of the substrate adjacent to the isolation layer pattern. A tunnel insulating layer and a charge trap layer are sequentially formed on the substrate. The tunnel insulating layer and the charge trap layer are patterned to form an isolated island-shaped tunnel insulating layer pattern and an isolated island-shaped charge trap layer pattern by etching defined regions of the substrate, the isolation layer pattern, the tunnel insulating layer, and the charge trap layer until a top surface of the charge trap layer that is disposed on a bottom surface of the recess unit is aligned with a top surface of the isolation layer pattern. A blocking insulating layer is formed that covers the charge trap layer pattern, the isolation layer pattern, and a defined region of the substrate interposed between the charge trap patterns. A gate electrode pattern is formed on the blocking insulating layer to face the charge trap layer pattern. This manufacturing process may reduce charge spreading between unit memory cells and/or may prevent/avoid reduction in the breakdown voltage of the blocking insulating layer.
摘要翻译：一些方法涉及制造电荷陷阱型非易失性存储器件。可以形成在衬底中沿第一方向延伸的隔离层图案。通过使邻近隔离层图案的基板的暴露表面凹陷而在基板中形成凹部单元。隧道绝缘层和电荷陷阱层依次形成在基板上。图案化隧道绝缘层和电荷陷阱层，通过蚀刻衬底的限定区域，隔离层图案，隧道绝缘层，隔离层状图案，隔离层状图案，隧道绝缘层，并且电荷陷阱层直到设置在凹陷单元的底表面上的电荷陷阱层的顶表面与隔离层图案的顶表面对准。形成了覆盖电荷陷阱层图案，隔离层图案和插入在电荷阱图案之间的基板的限定区域的阻挡绝缘层。在阻挡绝缘层上形成面对电荷陷阱层图案的栅电极图案。该制造过程可以减小单元存储单元之间的电荷扩展和/或可以防止/避免阻塞绝缘层的击穿电压的降低。

4. 发明申请

US20100001366A1 Semiconductor device having shared bit line structure and method of manufacturing the same 有权
标题翻译：具有共享位线结构的半导体器件及其制造方法
公开(公告)号：US20100001366A1
公开(公告)日：2010-01-07
申请号：US12457813
申请日：2009-06-22
申请人： Dong-hoon Jang , Young-bae Yoon , Hee-soo Kang , Young-seop Rah , Jeong-dong Choe
发明人： Dong-hoon Jang , Young-bae Yoon , Hee-soo Kang , Young-seop Rah , Jeong-dong Choe
IPC分类号： H01L29/06
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11519
摘要： A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.
摘要翻译：一种半导体器件，包括具有第一和第二有源区的衬底，所述第一和第二有源区设置在隔离结构的相对侧上;以及位线，其电耦合到所述隔离结构上的所述第一有源区区域和第二有源区域，并且电耦合到直接接触第一和第二有源区域中的至少一个的有源桥接图案，其中接触插塞电耦合到第一有源区域和第二有源区域，以及底表面所述有源桥模式位于所述第一和第二有源区的顶表面之下。

5. 发明申请

US20090302472A1 Non-volatile memory devices including shared bit lines and methods of fabricating the same 审中-公开
标题翻译：包括共享位线的非易失性存储器件及其制造方法
公开(公告)号：US20090302472A1
公开(公告)日：2009-12-10
申请号：US12453961
申请日：2009-05-28
申请人： Young-bae Yoon , Jeong-dong Choe , Hee-soo Kang , Dong-hoon Jang , Ki-hyun Kim
发明人： Young-bae Yoon , Jeong-dong Choe , Hee-soo Kang , Dong-hoon Jang , Ki-hyun Kim
IPC分类号： H01L23/52
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11548
摘要： Provided are non-volatile memory devices and methods of fabricating the same, including improved bit line and contact formation that may reduce resistance and parasitic capacitance, thereby reducing manufacturing costs and improving device performance. The non-volatile memory devices may include a substrate; a plurality of field regions formed on the substrate, each of the field regions including a homogeneous first field and a second field that is divided into two sub regions via a bridge region; an active region formed on the substrate and defined as having a string structure by the field regions, where at least two strings may be connected via one of the bridge regions; and a plurality of shared bit lines may be formed on the field regions and connected to the active region via bit line contacts, where the bit line contacts may be direct contacts.
摘要翻译：提供了非易失性存储器件及其制造方法，包括改进的位线和接触形成，其可以降低电阻和寄生电容，从而降低制造成本并提高器件性能。非易失性存储器件可以包括衬底; 形成在所述基板上的多个场区域，所述场区域中的每一个包括均匀的第一场和经由桥区域被划分为两个子区域的第二场; 形成在所述基板上的有源区，并且被定义为具有通过所述场区域的串结构，其中至少两个串可经由所述桥接区域之一连接; 并且可以在场区域上形成多个共享位线，并且经由位线触点连接到有源区，其中位线接触可以是直接接触。

6. 发明授权

US07615429B2 Methods of fabricating field effect transistors having multiple stacked channels 有权
标题翻译：制造具有多个堆叠通道的场效应晶体管的方法
公开(公告)号：US07615429B2
公开(公告)日：2009-11-10
申请号：US11948175
申请日：2007-11-30
申请人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
发明人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/823412 , H01L29/42356 , H01L29/42384 , H01L29/42392 , H01L29/66477 , H01L29/66545 , H01L29/66636 , H01L29/66772 , H01L29/66787 , H01L29/78 , H01L29/78642 , H01L29/78654 , H01L29/78696
摘要： Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.
摘要翻译：集成电路场效应晶体管器件包括在表面上具有表面和有源沟道图案的衬底。活动通道图案包括彼此堆叠并且彼此间隔开以限定相邻通道之间的至少一个通道的通道。栅电极围绕通道并延伸穿过至少一个通道。还提供了一对源极/漏极区域。通过在衬底的表面上形成预活性图案来制造集成电路场效应晶体管。预激活图案包括彼此交替堆叠的一系列通道间层和沟道层。在预活化图案的相对端处，在衬底上形成源极/漏极区域。选择性地去除通道间层以形成隧道。在隧道中形成栅电极并围绕通道。

7. 发明授权

US07534707B2 MOS Transistors having inverted T-shaped gate electrodes and fabrication methods thereof 失效
标题翻译：具有反相T形栅电极的MOS晶体管及其制造方法
公开(公告)号：US07534707B2
公开(公告)日：2009-05-19
申请号：US11560556
申请日：2006-11-16
申请人： Shin-Ae Lee , Dong-gun Park , Chang-sub Lee , Jeong-dong Choe , Sung-min Kim , Seong-ho Kim
发明人： Shin-Ae Lee , Dong-gun Park , Chang-sub Lee , Jeong-dong Choe , Sung-min Kim , Seong-ho Kim
IPC分类号： H01L21/3205
CPC分类号： H01L29/66583 , H01L21/28114 , H01L21/823842 , H01L21/82385 , H01L21/823864 , H01L29/42376 , H01L29/665 , H01L29/66537 , H01L29/66553
摘要： MOS transistors have an active region defined in a portion of a semiconductor substrate, a gate electrode on the active region, and drain and source regions in the substrate. First and second lateral protrusions extend from the lower portions of respective sidewalls of the gate electrode. The drain region has a first lightly-doped drain region under the first lateral protrusion, a second lightly-doped drain region adjacent the first lightly-doped drain region, and a heavily-doped drain region adjacent to the second lightly-doped drain region. The source region similarly has a first lightly-doped source region under the second lateral protrusion, a second lightly-doped source region adjacent the first lightly-doped source region, and a heavily-doped source region adjacent to the second lightly-doped source region. The second lightly-doped regions are deeper than the first lightly-doped regions, and the gate electrode may have an inverted T-shape.
摘要翻译： MOS晶体管具有限定在半导体衬底的一部分中的有源区，有源区上的栅电极和衬底中的漏极和源极区。第一和第二横向突起从栅电极的相应侧壁的下部延伸。漏极区域在第一横向突起下方具有第一轻掺杂漏极区域，与第一轻掺杂漏极区域相邻的第二轻掺杂漏极区域和与第二轻掺杂漏极区域相邻的重掺杂漏极区域。源极区域类似地在第二横向突起下方具有第一轻掺杂源极区域，与第一轻掺杂源极区域相邻的第二轻掺杂源极区域和与第二轻掺杂源极区域相邻的重掺杂源极区域。第二轻掺杂区域比第一轻掺杂区域深，并且栅电极可以具有倒置T形。

8. 发明授权

US07397131B2 Self-aligned semiconductor contact structures 失效
标题翻译：自对准半导体接触结构
公开(公告)号：US07397131B2
公开(公告)日：2008-07-08
申请号：US11396819
申请日：2006-04-03
申请人： Seong-Ho Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Sung-Min Kim , Shin-Ae Lee
发明人： Seong-Ho Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Sung-Min Kim , Shin-Ae Lee
IPC分类号： H01L29/772
CPC分类号： H01L21/76831 , H01L21/28114 , H01L21/76897 , H01L21/823425 , H01L21/823475 , H01L27/10888 , H01L27/10894 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window to define the sidewalls of the contact window.
摘要翻译：自对准接触结构及其形成方法包括具有相邻侧壁的选定的相邻栅电极，其被配置为朝向彼此成角度。可以使用能够延长接触窗口的长度以限定接触窗的侧壁的衬里层来保护栅电极的成角度的表面。

9. 发明申请

US20080090362A1 METHODS OF FABRICATING FIELD EFFECT TRANSISTORS HAVING MULTIPLE STACKED CHANNELS 有权
标题翻译：制作具有多个堆叠通道的场效应晶体管的方法
公开(公告)号：US20080090362A1
公开(公告)日：2008-04-17
申请号：US11948175
申请日：2007-11-30
申请人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
发明人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/823412 , H01L29/42356 , H01L29/42384 , H01L29/42392 , H01L29/66477 , H01L29/66545 , H01L29/66636 , H01L29/66772 , H01L29/66787 , H01L29/78 , H01L29/78642 , H01L29/78654 , H01L29/78696
摘要： Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.
摘要翻译：集成电路场效应晶体管器件包括在表面上具有表面和有源沟道图案的衬底。活动通道图案包括彼此堆叠并且彼此间隔开以限定相邻通道之间的至少一个通道的通道。栅电极围绕通道并延伸穿过至少一个通道。还提供了一对源极/漏极区域。通过在衬底的表面上形成预活性图案来制造集成电路场效应晶体管。预激活图案包括彼此交替堆叠的一系列通道间层和沟道层。在预活化图案的相对端处，在衬底上形成源极/漏极区域。选择性地去除通道间层以形成隧道。在隧道中形成栅电极并围绕通道。

10. 发明授权

US07214987B2 Semiconductor device having two different operation modes employing an asymmetrical buried insulating layer and method for fabricating the same 有权
标题翻译：具有采用不对称掩埋绝缘层的两种不同操作模式的半导体器件及其制造方法
公开(公告)号：US07214987B2
公开(公告)日：2007-05-08
申请号：US11011911
申请日：2004-12-13
申请人： Chang-Woo Oh , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe
发明人： Chang-Woo Oh , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe
IPC分类号： H01L27/12 , H01L27/01
CPC分类号： H01L27/10802 , H01L27/0214 , H01L27/10873 , H01L29/7841 , H01L29/78612
摘要： According to some embodiments, a semiconductor device includes a lower semiconductor substrate, an upper silicon pattern, and a MOS transistor. The MOS transistor includes a body region formed within the upper silicon pattern and source/drain regions separated by the body region. A buried insulating layer is interposed between the lower semiconductor substrate and the upper silicon pattern. A through plug penetrates the buried insulating layer and electrically connects the body region with the lower semiconductor substrate, the through plug positioned closer to one of the source/drain regions than the other source/drain region. At least some portion of the upper surface of the through plug is positioned outside a depletion layer when a source voltage is applied to the one of the source/drain regions, and the upper surface of the through plug is positioned inside the depletion layer when a drain voltage is applied to the one region.
摘要翻译：根据一些实施例，半导体器件包括下半导体衬底，上硅图案和MOS晶体管。 MOS晶体管包括形成在上硅图案内的主体区域和由身体区域分离的源极/漏极区域。掩埋绝缘层插入在下半导体衬底和上硅图案之间。穿通插塞穿透埋入的绝缘层并且电连接体区域与下半导体衬底，穿通插塞比另一个源极/漏极区域更靠近源极/漏极区域之一。当源极电压施加到源极/漏极区域之一时，贯通插塞的上表面的至少一部分位于耗尽层的外侧，并且当通过插塞的上表面位于耗尽层内时，漏极电压施加到该区域。

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