专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09564435B2 Semiconductor device including FinFETs having different gate structures and method of manufacturing the semiconductor device 有权
标题翻译：包括具有不同栅极结构的FinFET和半导体器件的制造方法的半导体器件
公开(公告)号：US09564435B2
公开(公告)日：2017-02-07
申请号：US14754400
申请日：2015-06-29
申请人： Eun-ae Chung , Jung-dal Choi , Toshiro Nakanishi , Yu-bin Kim , Gab-jin Nam , Dong-kyu Lee , Guangfan Jiao
发明人： Eun-ae Chung , Jung-dal Choi , Toshiro Nakanishi , Yu-bin Kim , Gab-jin Nam , Dong-kyu Lee , Guangfan Jiao
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392 , H01L27/088 , H01L21/8234
CPC分类号： H01L27/0886 , H01L21/823412 , H01L21/823431 , H01L27/1211
摘要： A semiconductor device includes a substrate having a logic device region including logic devices thereon, and an input/output (I/O) device region including I/O devices thereon adjacent the logic device region. A first fin field-effect transistor (FinFET) on the logic device region includes a first semiconductor fin protruding from the substrate, and a triple-gate structure having a first gate dielectric layer and a first gate electrode thereon. A second FinFET on the I/O device region includes a second semiconductor fin protruding from the substrate, and a double-gate structure having a second gate dielectric layer and a second gate electrode thereon. The first and second gate dielectric layers have different thicknesses. Related devices and fabrication methods are also discussed.
摘要翻译：半导体器件包括具有其上包括逻辑器件的逻辑器件区域的衬底，以及在其上邻近逻辑器件区域的包括I / O器件的输入/输出（I / O）器件区域。逻辑器件区域上的第一鳍状场效应晶体管（FinFET）包括从衬底突出的第一半导体鳍片，以及在其上具有第一栅极电介质层和第一栅极电极的三栅极结构。 I / O器件区域上的第二FinFET包括从衬底突出的第二半导体鳍片，以及在其上具有第二栅极介电层和第二栅电极的双栅极结构。第一和第二栅极电介质层具有不同的厚度。还讨论了相关设备和制造方法。

2. 发明申请

US20150214478A1 VARIABLE RESISTANCE MEMORY DEVICES 有权
标题翻译：可变电阻存储器件
公开(公告)号：US20150214478A1
公开(公告)日：2015-07-30
申请号：US14457439
申请日：2014-08-12
申请人： Jung-Moo Lee , Youn-Seon Kang , Seung-Jae Jung , Jung-Dal Choi
发明人： Jung-Moo Lee , Youn-Seon Kang , Seung-Jae Jung , Jung-Dal Choi
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/1233 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/08 , H01L45/1675
摘要： A variable resistance memory device includes a plurality of first conductive lines, a plurality of second conductive lines, a plurality of memory cells, a plurality of first air gaps and a plurality of second air gaps. The first conductive line extends in a first direction. The second conductive line is over the first conductive line and extends in a second direction crossing the first direction. The memory cell includes a variable resistance device. The memory cell is located at an intersection region of the first conductive line and the second conductive line. The first air gap extends in the first direction between the memory cells. The second air gap extends in the second direction between the memory cells.
摘要翻译：可变电阻存储器件包括多个第一导线，多个第二导线，多个存储单元，多个第一气隙和多个第二气隙。第一导线沿第一方向延伸。第二导线在第一导线上方并且沿与第一方向交叉的第二方向延伸。存储单元包括可变电阻器件。存储单元位于第一导线和第二导线的交叉区域。第一气隙在存储单元之间沿第一方向延伸。第二气隙沿第二方向在存储单元之间延伸。

3. 发明授权

US08629489B2 Nonvolatile memory devices 有权
标题翻译：非易失性存储器件
公开(公告)号：US08629489B2
公开(公告)日：2014-01-14
申请号：US13357350
申请日：2012-01-24
申请人： Chang-Hyun Lee , Jung-Dal Choi
发明人： Chang-Hyun Lee , Jung-Dal Choi
IPC分类号： H01L29/76
CPC分类号： H01L27/1052 , G11C16/0483 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers.
摘要翻译：非易失性存储器件包括串选择晶体管，多个存储单元晶体管和与串选择晶体管和多个存储单元晶体管串联电连接的接地选择晶体管。在存储单元晶体管的沟道和源极/漏极区的边界处形成第一杂质层。相对于存储单元晶体管的源/漏区，第一杂质层掺杂有相反导电类型的杂质。第二杂质层形成在串选择晶体管的沟道和漏极区之间的边界处，并且在地选择晶体管的沟道和源极区之间形成。第二杂质层掺杂有与第一杂质层相同的导电类型杂质，并且具有比第一杂质层更高的杂质浓度。

4. 发明授权

US08588001B2 Integrated circuit memory devices having vertically arranged strings of memory cells therein and methods of operating same 有权
标题翻译：具有垂直排列的存储器单元串的集成电路存储器件及其操作方法
公开(公告)号：US08588001B2
公开(公告)日：2013-11-19
申请号：US13181037
申请日：2011-07-12
申请人： Jae-Sung Sim , Jung-Dal Choi
发明人： Jae-Sung Sim , Jung-Dal Choi
IPC分类号： G11C16/04
CPC分类号： H01L27/11551 , G11C5/02 , G11C16/0483 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/11578
摘要： Nonvolatile memory devices include a first NAND-type string of EEPROM cells having a first plurality of string selection transistors therein electrically connected in series within the string. This first plurality of string selection transistors includes a first plurality of depletion-mode transistors and a first enhancement-mode transistor. A second NAND-type string of EEPROM cells is provided with a second plurality of string selection transistors therein that are electrically connected in series. The second plurality of string selection transistors includes a second plurality of depletion-mode transistors and a second enhancement-mode transistor. The first enhancement-mode transistor is stacked vertically relative to one of the second plurality of depletion-mode transistors and the second enhancement-mode transistor is stacked vertically relative to one of the first plurality of depletion-mode transistors. A first string selection plug is configured to electrically connect gate electrodes of the first enhancement-mode transistor and one of the second plurality of depletion-mode transistors.
摘要翻译：非易失性存储器件包括第一NAND型EEPROM单元串，其具有在串中串联电连接的第一多个串选择晶体管。该第一多个串选择晶体管包括第一多个耗尽型晶体管和第一增强型晶体管。 EEPROM单元的第二NAND型串提供有串联电连接的第二多个串选择晶体管。第二多个串选择晶体管包括第二多个耗尽型晶体管和第二增强型晶体管。第一增强型晶体管相对于第二多个耗尽型晶体管中的一个垂直堆叠，并且第二增强型晶体管相对于第一多个耗尽型晶体管之一垂直堆叠。第一串选择插头被配置为电连接第一增强型晶体管的栅极和第二多个耗尽型晶体管中的一个。

5. 发明申请

US20130270624A1 GATE STRUCTURE IN NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件中的门结构
公开(公告)号：US20130270624A1
公开(公告)日：2013-10-17
申请号：US13759195
申请日：2013-02-05
申请人： Jang-Gn YUN , Jung-Dal CHOI , Kwang-Soo SEOL
发明人： Jang-Gn YUN , Jung-Dal CHOI , Kwang-Soo SEOL
IPC分类号： H01L29/792
CPC分类号： H01L29/7926 , H01L21/28282 , H01L27/1157 , H01L27/11582 , H01L29/66833 , H01L29/792
摘要： A gate structure of a non-volatile memory device and a method of forming the same including a tunnel oxide layer pattern, a charge trap layer pattern, a blocking dielectric layer pattern having the uppermost layer including a material having a first dielectric constant greater than that of a material included in the tunnel oxide layer pattern, and first and second conductive layer patterns. The gate structure includes a first spacer to cover at least the sidewall of the second conductive layer pattern. The gate structure includes a second spacer covering the sidewall of the first spacer and the sidewall of the first conductive layer pattern and including a material having a second dielectric constant equal to or greater than the first dielectric constant. In the non-volatile memory device including the gate structure, erase saturation caused by back tunneling is reduced.
摘要翻译：非易失性存储器件的栅极结构及其形成方法，其包括隧道氧化物层图案，电荷陷阱层图案，阻挡介电层图案，其最上层包括第一介电常数大于其的介电常数的材料。包括在隧道氧化物层图案中的材料，以及第一和第二导电层图案。栅极结构包括至少覆盖第二导电层图案的侧壁的第一间隔物。栅极结构包括覆盖第一间隔物的侧壁和第一导电层图案的侧壁的第二间隔物，并且包括具有等于或大于第一介电常数的第二介电常数的材料。在包括栅极结构的非易失性存储器件中，由于后部隧道引起的擦除饱和度降低。

6. 发明授权

US08329574B2 Methods of fabricating flash memory devices having shared sub active regions 有权
标题翻译：制造具有共享子有源区的闪存器件的方法
公开(公告)号：US08329574B2
公开(公告)日：2012-12-11
申请号：US13230978
申请日：2011-09-13
申请人： Jong-Sun Sel , Jung-Dal Choi
发明人： Jong-Sun Sel , Jung-Dal Choi
IPC分类号： H01L21/44
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , Y10S257/905
摘要： Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region.
摘要翻译：闪存器件包括在衬底中的一对细长的，紧密间隔的主要有源区。亚基活性区域还设置在基底中，在一对细长的，紧密间隔开的主活性区域之间延伸。位线接触插头设置在子有源区上并且电接触，并且至少与次有源区一样宽。在远离副有源区域的位线接触插头上提供细长的位线并且电接触。

7. 发明授权

US08248853B2 Methods of programming non-volatile flash memory devices by applying a higher voltage level to a selected word line than to a word line neighboring the selected word line 有权
标题翻译：通过对所选择的字线施加比毗邻所选字线的字线更高的电压电平来对非易失性闪存器件进行编程的方法
公开(公告)号：US08248853B2
公开(公告)日：2012-08-21
申请号：US12590701
申请日：2009-11-12
申请人： Jae Duk Lee , Soon Moon Jung , Jung Dal Choi
发明人： Jae Duk Lee , Soon Moon Jung , Jung Dal Choi
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In a method of programming a non-volatile memory device, a first voltage is applied to a selected word line corresponding to a selected memory cell transistor of a selected transistor string to be programmed; a second voltage is applied to a neighboring word line neighboring the selected word line and corresponding to a neighboring transistor of the selected transistor string, wherein the first voltage is greater than the second voltage, the application of the first and second voltages to the selected and neighboring word lines respectively causing electrons to be generated by an electric field formed between the neighboring transistor and the selected memory cell transistor, the electrons accelerating toward the selected memory cell transistor and injecting into a charge storage layer of the selected memory cell transistor; wherein the neighboring transistor is positioned between the selected memory cell transistor and one of a ground select transistor and a string select transistor, and the first voltage is applied to unselected word lines corresponding to unselected memory cell transistors of the selected transistor string positioned between the selected memory cell transistor and the other of the ground select transistor and the string select transistor.
摘要翻译：在编程非易失性存储器件的方法中，将第一电压施加到对应于要编程的所选择的晶体管串的选定存储单元晶体管的选定字线; 第二电压被施加到与所选择的字线相邻并且对应于所选择的晶体管串的相邻晶体管的相邻字线，其中第一电压大于第二电压，将第一和第二电压施加到所选择的和分别使相邻的晶体管与所选择的存储单元晶体管之间形成的电场产生电子的相邻字线，电子向所选择的存储单元晶体管加速并注入到所选存储单元晶体管的电荷存储层中; 其中所述相邻晶体管位于所选择的存储单元晶体管和接地选择晶体管和串选择晶体管中的一个之间，并且所述第一电压被施加到对应于所选择的晶体管串的未选择存储单元晶体管的未选择字线，存储单元晶体管和另一个接地选择晶体管和串选择晶体管。

8. 发明授权

US08198157B2 Methods of forming non-volatile memory devices including dummy word lines 有权
标题翻译：形成包括虚拟字线的非易失性存储器件的方法
公开(公告)号：US08198157B2
公开(公告)日：2012-06-12
申请号：US13236913
申请日：2011-09-20
申请人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
发明人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
IPC分类号： H01L21/82 , H01L21/336 , H01L21/4763 , H01L21/44
CPC分类号： G11C16/0483 , G11C16/3427
摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，有源区上的第一存储单元串和有源区上的第二存储单元串。第一存储单元串可以包括与第一地选择线和第一串选择线之间的有源区域交叉的第一多个字线，并且可以在第一多个字线中相邻的字线之间提供约相同的第一间隔。第二存储单元串可以包括与第二接地选择线和第二串选择线之间的有源区域交叉的第二多个字线，并且可以在相邻的第二多个字线之间提供约相同的第一间隔。还讨论了相关方法。

9. 发明申请

US20120045890A1 Methods Of Forming Non-Volatile Memory Devices Including Dummy Word Lines 有权
标题翻译：形成包含虚拟字线的非易失性存储器件的方法
公开(公告)号：US20120045890A1
公开(公告)日：2012-02-23
申请号：US13236913
申请日：2011-09-20
申请人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
发明人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
IPC分类号： H01L21/28
CPC分类号： G11C16/0483 , G11C16/3427
摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，有源区上的第一存储单元串和有源区上的第二存储单元串。第一存储单元串可以包括与第一地选择线和第一串选择线之间的有源区域交叉的第一多个字线，并且可以在第一多个字线中相邻的字线之间提供约相同的第一间隔。第二存储单元串可以包括与第二接地选择线和第二串选择线之间的有源区域交叉的第二多个字线，并且可以在相邻的第二多个字线之间提供约相同的第一间隔。还讨论了相关方法。

10. 发明授权

US08048746B2 Method of making flash memory cells and peripheral circuits having STI, and flash memory devices and computer systems having the same 失效
公开(公告)号：US08048746B2
公开(公告)日：2011-11-01
申请号：US12979890
申请日：2010-12-28
申请人： Jin-Taek Park , Young-Woo Park , Jang-Hyun You , Jung-Dal Choi
发明人： Jin-Taek Park , Young-Woo Park , Jang-Hyun You , Jung-Dal Choi
IPC分类号： H01L21/336
CPC分类号： H01L27/11573 , H01L27/11526 , H01L27/11546 , H01L27/11592 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel barrier layer may comprise a part of the gate dielectric of the HVTs. The tunnel barrier layer may constitute the entire gate dielectric of the HVTs. The corresponding tunnel barrier layer may be formed between or upon shallow trench isolation (STIs). Therefore, the manufacturing efficiency of a driver chip IC may be increased.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式