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1. 发明申请

US20060284265A1 High voltage N-channel LDMOS devices built in a deep submicron CMOS process 审中-公开
公开(公告)号：US20060284265A1
公开(公告)日：2006-12-21
申请号：US11509847
申请日：2006-08-25
申请人： Gregorio Spadea
发明人： Gregorio Spadea
IPC分类号： H01L29/76
CPC分类号： H01L29/7816 , H01L29/0653 , H01L29/0847 , H01L29/0878
摘要： A novel Laterally Diffused NMOS device is described. With proper design the drain terminal of this device can be raised to a much higher voltage that the maximum allowed gate voltage of the CMOS technology into which the device is built. The device can be built in a conventional deep submicron CMOS technology as used for the 0.25 um node and beyond without additional masks or dedicated processing steps. When a deep N-well mask and ion implantation is added to the process, the device can be operated with a body voltage positive above ground. This device can be used like a conventional LDMOS for circuits which require a device capable of switching voltages which exceed the rating of conventional CMOS devices by using as low voltage input signal.

2. 发明授权

US06451652B1 Method for forming an EEPROM cell together with transistor for peripheral circuits 有权
标题翻译：用于与外围电路晶体管一起形成EEPROM单元的方法
公开(公告)号：US06451652B1
公开(公告)日：2002-09-17
申请号：US09656730
申请日：2000-09-07
申请人： John Caywood , Gregorio Spadea
发明人： John Caywood , Gregorio Spadea
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： A method for forming an EEPROM cell together with transistors for peripheral circuits is disclosed. The method results in having a predetermined amount of material remaining proximate to the edge of the electrode, thereby forming a structure that extends a short distance beyond the sides of the electrode. An additional method for forming an trilayer EEPROM cell together with transistors for peripheral circuits is also disclosed, which results trilayer layer being restricted to covering the electrode and a small proximate region extending over the substrate surface. Two shoulders may also be etched into the sidewalls of the oxide layer which lie along the edges of said electrode.
摘要翻译：公开了一种与外围电路晶体管一起形成EEPROM单元的方法。该方法导致具有在电极边缘附近保留的预定量的材料，从而形成延伸超过电极侧面的短距离的结构。还公开了用于与外围电路的晶体管一起形成三层EEPROM单元的附加方法，这导致三层被限制为覆盖电极和在衬底表面上延伸的小的邻近区域。也可以在沿着所述电极的边缘的氧化物层的侧壁中蚀刻两个肩部。

3. 再颁专利

USRE40976E1 Common source EEPROM and flash memory 有权
公开(公告)号：USRE40976E1
公开(公告)日：2009-11-17
申请号：US11198860
申请日：2005-08-04
申请人： Albert Bergemont , Gregorio Spadea
发明人： Albert Bergemont , Gregorio Spadea
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/0425
摘要： A nonvolatile memory array is arranged as a plurality of rows and columns of memory cell transistors. The sources of the memory cell transistors in each row of the array are electrically coupled together. The control gates of the memory cell transistors associated with a row in the array are coupled to a wordline associated with that row. The drains of the memory cell transistors in a column of the array are coupled to a bitline associated with that column. A source transistor is associated with each row and has its source coupled to a common source line, its drain coupled to the sources of all memory cell transistors in that row, and a gate coupled to the wordline. An array of split-gate nonvolatile memory cells is also disclosed.

4. 发明授权

US07332769B2 Non-volatile memory arrangement having nanocrystals 失效
标题翻译：具有纳米晶体的非易失性存储器装置
公开(公告)号：US07332769B2
公开(公告)日：2008-02-19
申请号：US11204933
申请日：2005-08-17
申请人： Gregorio Spadea
发明人： Gregorio Spadea
IPC分类号： H01L29/792
CPC分类号： H01L29/7393
摘要： The amount of current flowing in the bitline during reading of a memory cell which is in the conductive state, hereinafter called the memory cell current, can be amplified manifold by changing the above mentioned select transistors to a novel device which is described in detail. The increase of the area of the said memory arrays due to the replacement of said select transistor with the novel device is very small. In addition the novel device can be built within the pitch of said select transistor, which is the pitch of the bitline. The novel device can be used in many types of semiconductor memories, as described in the various embodiments. Static random access semiconductor memories can also benefit from the use of the novel devices.
摘要翻译：在读取导通状态的存储单元（以下称为存储单元电流）期间在位线中流动的电流量可以通过将上述选择晶体管改变为详细描述的新型器件而被放大。由于用新型器件替换所述选择晶体管，所述存储器阵列的面积的增加非常小。此外，新颖器件可以构建在作为位线的间距的所述选择晶体管的间距内。如在各种实施例中所描述的，该新型器件可用于多种类型的半导体存储器中。静态随机存取半导体存储器也可以受益于新型器件的使用。

5. 发明申请

US20050110073A1 Low voltage EEPROM memory arrays 失效
标题翻译：低电压EEPROM存储器阵列
公开(公告)号：US20050110073A1
公开(公告)日：2005-05-26
申请号：US10896152
申请日：2004-07-20
申请人： Gregorio Spadea
发明人： Gregorio Spadea
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , G11C7/02
CPC分类号： G11C16/0483 , G11C16/0416 , G11C16/0433 , G11C2211/565 , H01L27/115 , H01L27/11521
摘要： A non-volatile memory array includes memory cells connected in a common source arrangement and formed in columns of isolated well regions so that Fowler-Nordheim tunneling is used for both write and erase operations of the memory cells. The memory arrays can be formed as NOR arrays or NAND arrays. In one embodiment, the memory array of the present invention is formed as a byte alterable EEPROM with parallel access. In another embodiment, an insulated gate bipolar transistor (IGBT) is coupled to the memory cells to increase the cell read current of the memory array. When the memory array incorporates IGBTs on the bitlines, the cell read current becomes independent of the wordline voltages. Thus, the memory array of the present invention can be operated at low voltages. The use of IGBTs in the memory array of the present invention enables formation of embedded non-volatile memories in low-voltage digital integrated circuits.
摘要翻译：非易失性存储器阵列包括以公共源装置连接并且形成在隔离阱区域的列中的存储器单元，使得Fowler-Nordheim隧道用于存储器单元的写入和擦除操作。存储器阵列可以形成为NOR阵列或NAND阵列。在一个实施例中，本发明的存储器阵列形成为具有并行访问的字节可变EEPROM。在另一个实施例中，绝缘栅双极晶体管（IGBT）耦合到存储单元以增加存储器阵列的单元读取电流。当存储器阵列在位线上并入IGBT时，单元读取电流与字线电压无关。因此，本发明的存储器阵列可以在低电压下工作。在本发明的存储器阵列中使用IGBT能够在低压数字集成电路中形成嵌入式非易失性存储器。

6. 发明申请

US20080128794A1 Non-Volatile Memory Including Insulated Gate Bipolar Transistors And Charge Trapping Layer Containing Silicon and Nitrogen 审中-公开
标题翻译：包括绝缘栅双极晶体管和含有硅和氮的电荷捕获层的非易失性存储器
公开(公告)号：US20080128794A1
公开(公告)日：2008-06-05
申请号：US12029368
申请日：2008-02-11
申请人： Gregorio Spadea
发明人： Gregorio Spadea
IPC分类号： H01L29/792
CPC分类号： H01L29/7393
摘要： A memory block of a semiconductor memory array where the semiconductor memory array is a NOR array, a NAND array, or an AND array includes a bit line, memory cells where each memory cell has a floating gate including a charge trapping layer containing silicon and nitrogen, a metal-oxide-semiconductor select transistor that separates said bit line and said memory cells, a semiconductor region enclosed within the drain of said select transistor with a conductivity type that is opposite to that of said drain, and a semiconductor well region shared by said select transistor and said memory cells.
摘要翻译：半导体存储器阵列是NOR阵列，NAND阵列或AND阵列的半导体存储器阵列的存储块包括位线，存储器单元，其中每个存储单元具有包括含有硅和氮的电荷捕获层的浮置栅极，分离所述位线和所述存储单元的金属氧化物半导体选择晶体管，封装在所述选择晶体管的漏极内的半导体区域，所述半导体区域具有与所述漏极的导电类型相反的导电类型，以及半导体阱区域所述选择晶体管和所述存储单元。

7. 发明申请

US20070040209A1 Novel applications for insulated gate bipolar transistors 失效
标题翻译：绝缘栅双极晶体管的新应用
公开(公告)号：US20070040209A1
公开(公告)日：2007-02-22
申请号：US11204933
申请日：2005-08-17
申请人： Gregorio Spadea
发明人： Gregorio Spadea
IPC分类号： G11C11/34 , H01L29/788
CPC分类号： H01L29/7393
摘要： The amount of current flowing in the bitline during reading of a memory cell which is in the conductive state, hereinafter called the memory cell current, can be amplified manifold by changing the above mentioned select transistors to a novel device which is described in detail. The increase of the area of the said memory arrays due to the replacement of said select transistor with the novel device is very small. In addition the novel device can be built within the pitch of said select transistor, which is the pitch of the bitline. The novel device can be used in many types of semiconductor memories, as described in the various embodiments. Static random access semiconductor memories can also benefit from the use of the novel devices
摘要翻译：在读取导通状态的存储单元（以下称为存储单元电流）期间在位线中流动的电流量可以通过将上述选择晶体管改变为详细描述的新型器件而被放大。由于用新型器件替换所述选择晶体管，所述存储器阵列的面积的增加非常小。此外，新颖器件可以构建在作为位线的间距的所述选择晶体管的间距内。如在各种实施例中所描述的，该新型器件可用于多种类型的半导体存储器中。静态随机存取半导体存储器也可以受益于新型器件的使用

8. 发明授权

US4224733A Ion implantation method 失效
标题翻译：离子注入法
公开(公告)号：US4224733A
公开(公告)日：1980-09-30
申请号：US840793
申请日：1977-10-11
申请人： Gregorio Spadea
发明人： Gregorio Spadea
IPC分类号： H01L27/092 , H01L21/265 , H01L21/266 , H01L21/8234 , H01L21/8238 , H01L27/06 , H01L29/78 , B01J17/00
CPC分类号： H01L21/266 , H01L21/265 , H01L21/2652 , H01L21/823857 , Y10S148/141 , Y10S148/147
摘要： Ions are implanted into a body, such as semiconductor substrate material, through one or more covering layers formed over the body. A thin conductive film is in contact with the covering layer prior to the ion implantation. The ions are implanted into the material through the thin conductive film. The conductive film functions to conduct away any charge which tends to accumulate in the covering layer. The conductive film thereby prevents a charge accumulation which would tend to discharge through and cause damage to the covering layer. The method is particularly useful for fabricating MOS and CMOS semiconductor devices.
摘要翻译：离子通过形成在身体上的一个或多个覆盖层植入体内，例如半导体衬底材料。在离子注入之前，薄的导电膜与覆盖层接触。通过薄导电膜将离子注入到材料中。导电膜用于导致倾向于积聚在覆盖层中的任何电荷。因此，导电膜可以防止电荷积聚，这种电荷积聚将倾向于通过并且对覆盖层造成损害。该方法对于制造MOS和CMOS半导体器件特别有用。

9. 发明授权

US06606265B2 Common source EEPROM and flash memory 有权
公开(公告)号：US06606265B2
公开(公告)日：2003-08-12
申请号：US10002607
申请日：2001-10-30
申请人： Albert Bergemont , Gregorio Spadea
发明人： Albert Bergemont , Gregorio Spadea
IPC分类号： G11C1604
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/0425
摘要： A nonvolatile memory array is arranged as a plurality of rows and columns of memory cell transistors. The sources of the memory cell transistors in each row of the array are electrically coupled together. The control gates of the memory cell transistors associated with a row in the array are coupled to a wordline associated with that row. The drains of the memory cell transistors in a column of the array are coupled to a bitline associated with that column. A source transistor is associated with each row and has its source coupled to a common source line, its drain coupled to the sources of all memory cell transistors in that row, and a gate coupled to the wordline. An array of split-gate nonvolatile memory cells is also disclosed.

10. 发明授权

US4047285A Self-aligned CMOS for bulk silicon and insulating substrate device 失效
标题翻译：用于体硅和绝缘衬底器件的自对准CMOS
公开(公告)号：US4047285A
公开(公告)日：1977-09-13
申请号：US697290
申请日：1976-06-17
申请人： Gregorio Spadea
发明人： Gregorio Spadea
IPC分类号： H01L21/033 , H01L21/8238 , H01L27/092 , H01L27/12 , H01L29/08 , H01L29/786 , B01J17/00
CPC分类号： H01L29/78696 , H01L21/033 , H01L21/823814 , H01L27/0927 , H01L27/12 , H01L29/0847
摘要： The method for fabrication of a self-aligned gate CMOS structure which employs no additional masking steps as compared to the standard CMOS fabrication process, this improved process providing the advantages of self-alignment between the N+ and P+ source and drain diffusions with respect to their gate regions, and metal contact openings which do not overlap the edges of the P+ or N+ source and drain regions. The self-aligning gate region is defined by a silicon nitride gate layer. Several embodiments of the novel process are described.
摘要翻译：与标准CMOS制造工艺相比，制造自对准栅极CMOS结构的方法不采用额外的掩模步骤，该改进的工艺提供了N +和P +源极和漏极扩散之间的自对准优点，相对于它们栅极区域和不与P +或N +源极和漏极区域的边缘重叠的金属接触开口。自对准栅极区域由氮化硅栅极层限定。描述新颖方法的几个实施方案。

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