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1. 发明授权

US07944750B1 Multi-programmable non-volatile memory cell 有权
标题翻译：多可编程非易失性存储单元
公开(公告)号：US07944750B1
公开(公告)日：2011-05-17
申请号：US12288762
申请日：2008-10-22
申请人： Albert Bergemont , David Kuan-Yu Liu , Venkatraman Prabhakar , Sridevi Rajagopalan Schmidt
发明人： Albert Bergemont , David Kuan-Yu Liu , Venkatraman Prabhakar , Sridevi Rajagopalan Schmidt
IPC分类号： G11C16/04
CPC分类号： G11C16/0408 , G11C16/10
摘要： A non-volatile memory device and method for manufacture and programing which does not require a control gate for the programing or erasure of the device. The memory device is comprised of two wells with the opposite conductivity type of the semiconductor body. In one of the wells is a source and drain well of the same conductivity type as of the body. A oxide is formed on the surface of the body on which a floating gate is formed. Specific voltages are applied to the source, drain, first well and second well region to program, erase and read the memory device.
摘要翻译：用于制造和编程的非易失性存储器件和方法，其不需要用于编程或擦除器件的控制栅极。存储器件由具有相反导电类型的半导体本体的两个阱构成。其中一个井是与身体相同的导电类型的源极和漏极井。在其上形成有浮动栅极的主体的表面上形成氧化物。将特定电压施加到源极，漏极，第一阱和第二阱区域以对存储器件进行编程，擦除和读取。

2. 发明授权

US07535758B2 One or multiple-times programmable device 有权
标题翻译：一个或多个可编程器件
公开(公告)号：US07535758B2
公开(公告)日：2009-05-19
申请号：US11703922
申请日：2007-02-06
申请人： Albert Bergemont , David Kuan-Yu Liu , Venkatraman Prabhakar
发明人： Albert Bergemont , David Kuan-Yu Liu , Venkatraman Prabhakar
IPC分类号： G11C16/04
CPC分类号： H01L29/7885 , G11C16/0416 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： Methods and apparatus, including computer program products, for a one or multiple-times programmable memory device. A semiconductor may include an active region of a substrate, a thin oxide layer over a substrate, a first and second polysilicon layer, and a first and second metal layer. The first polysilicon layer may have a floating gate, the active region may be substantially perpendicular to the floating gate, and the second polysilicon layer may include a control gate. The first metal layer may include a bit line connected to a first n-diffused region, where the bit line is substantially perpendicular to the floating gate. The second metal layer may include a word line and source line. The word line may be connected to the control gate, and the source line may be connected to a second n-diffused region. The thin gate oxide may have a thickness between 65 and 75 angstroms.
摘要翻译：用于一次或多次可编程存储器件的方法和装置，包括计算机程序产品。半导体可以包括衬底的有源区，衬底上的薄氧化层，第一和第二多晶硅层以及第一和第二金属层。第一多晶硅层可以具有浮置栅极，有源区可以基本上垂直于浮置栅极，并且第二多晶硅层可以包括控制栅极。第一金属层可以包括连接到第一n扩散区域的位线，其中位线基本上垂直于浮动栅极。第二金属层可以包括字线和源极线。字线可以连接到控制栅极，并且源极线可以连接到第二n扩散区域。薄栅氧化物可以具有65和75埃之间的厚度。

3. 发明申请

US20080186773A1 One or multiple-times programmable device 有权
标题翻译：一个或多个可编程器件
公开(公告)号：US20080186773A1
公开(公告)日：2008-08-07
申请号：US11703922
申请日：2007-02-06
申请人： Albert Bergemont , David Kuan-Yu Liu , Venkatraman Prabhakar
发明人： Albert Bergemont , David Kuan-Yu Liu , Venkatraman Prabhakar
IPC分类号： G11C16/06 , H01L21/336 , H01L29/788
CPC分类号： H01L29/7885 , G11C16/0416 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： Methods and apparatus, including computer program products, for a one or multiple-times programmable memory device. A semiconductor may include an active region of a substrate, a thin oxide layer over a substrate, a first and second polysilicon layer, and a first and second metal layer. The first polysilicon layer may have a floating gate, the active region may be substantially perpendicular to the floating gate, and the second polysilicon layer may include a control gate. The first metal layer may include a bit line connected to a first n-diffused region, where the bit line is substantially perpendicular to the floating gate. The second metal layer may include a word line and source line. The word line may be connected to the control gate, and the source line may be connected to a second n-diffused region. The thin gate oxide may have a thickness between 65 and 75 angstroms.
摘要翻译：用于一次或多次可编程存储器件的方法和装置，包括计算机程序产品。半导体可以包括衬底的有源区，衬底上的薄氧化层，第一和第二多晶硅层以及第一和第二金属层。第一多晶硅层可以具有浮置栅极，有源区可以基本上垂直于浮置栅极，并且第二多晶硅层可以包括控制栅极。第一金属层可以包括连接到第一n扩散区域的位线，其中位线基本上垂直于浮动栅极。第二金属层可以包括字线和源极线。字线可以连接到控制栅极，并且源极线可以连接到第二n扩散区域。薄栅氧化物可以具有65和75埃之间的厚度。

4. 发明申请

US20090014772A1 EEPROM MEMORY CELL WITH FIRST-DOPANT-TYPE CONTROL GATE TRANSISTOR, AND SECOND-DOPANT TYPE PROGRAM/ERASE AND ACCESS TRANSISTORS FORMED IN COMMON WELL 有权
标题翻译：具有第一种类型控制栅极晶体管的EEPROM存储器单元和通常形成的第二种类型的程序/擦除和访问晶体管
公开(公告)号：US20090014772A1
公开(公告)日：2009-01-15
申请号：US12233294
申请日：2008-09-18
申请人： Nirmal Ratnakumar , Venkatraman Prabhakar , David Kuan-Yu Liu
发明人： Nirmal Ratnakumar , Venkatraman Prabhakar , David Kuan-Yu Liu
IPC分类号： H01L29/788
CPC分类号： G11C16/0441 , G11C16/3427 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell.
摘要翻译：一种包括多个存储单元的存储器件，每个存储器单元具有与编程/擦除PMOS晶体管共享浮置栅极的控制栅极NMOS晶体管，该晶体管又与访问PMOS晶体管串联连接。存储单元形成在形成在P基板中的公共N阱中，NMOS晶体管形成在p掺杂的凹穴或基底中。编程/擦除PMOS包括栅极和形成在N阱中的第一和第二P +掺杂区域，其中第一P +区域电连接到相应的位线。存取PMOS包括栅极和形成在N阱内的第一和第二P +区，其中第一P +区电连接到编程/擦除PMOS的第二P +区，栅极电连接到相应的字线。控制栅极NMOS包括源极，漏极和栅极，其中源极和第三漏极以及p掺杂的阱电连接到相应的控制栅极线，并且栅极电连接到编程/擦除的栅极 PMOS，形成电池的浮动栅极。

5. 发明申请

US20080273392A1 METHOD OF PROGRAMMING A SELECTED MEMORY CELL 有权
标题翻译：编程选择的记忆细胞的方法
公开(公告)号：US20080273392A1
公开(公告)日：2008-11-06
申请号：US12168858
申请日：2008-07-07
申请人： Nirmal Ratnakumar , Venkatraman Prabhakar , David Kuan-Yu Liu
发明人： Nirmal Ratnakumar , Venkatraman Prabhakar , David Kuan-Yu Liu
IPC分类号： G11C16/06
CPC分类号： G11C16/0441 , G11C16/3427 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell.
摘要翻译：一种包括多个存储单元的存储器件，每个存储器单元具有与编程/擦除PMOS晶体管共享浮置栅极的控制栅极NMOS晶体管，该晶体管又与访问PMOS晶体管串联连接。存储单元形成在形成在P基板中的公共N阱中，NMOS晶体管形成在p掺杂的凹穴或基底中。编程/擦除PMOS包括栅极和形成在N阱中的第一和第二P +掺杂区域，其中第一P +区域电连接到相应的位线。存取PMOS包括栅极和形成在N阱内的第一和第二P +区，其中第一P +区电连接到编程/擦除PMOS的第二P +区，栅极电连接到相应的字线。控制栅极NMOS包括源极，漏极和栅极，其中源极和第三漏极以及p掺杂的阱电连接到相应的控制栅极线，并且栅极电连接到编程/擦除的栅极 PMOS，形成电池的浮动栅极。

6. 发明申请

US20080273401A1 METHOD OF ERASING A BLOCK OF MEMORY CELLS 有权
标题翻译：擦除记忆细胞块的方法
公开(公告)号：US20080273401A1
公开(公告)日：2008-11-06
申请号：US12168863
申请日：2008-07-07
申请人： Nirmal Ratnakumar , Venkatraman Prabhakar , David Kuan-Yu Liu
发明人： Nirmal Ratnakumar , Venkatraman Prabhakar , David Kuan-Yu Liu
IPC分类号： G11C16/16
CPC分类号： G11C16/0441 , G11C16/3427 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell.
摘要翻译：一种包括多个存储单元的存储器件，每个存储器单元具有与编程/擦除PMOS晶体管共享浮置栅极的控制栅极NMOS晶体管，该晶体管又与访问PMOS晶体管串联连接。存储单元形成在形成在P基板中的公共N阱中，NMOS晶体管形成在p掺杂的凹穴或基底中。编程/擦除PMOS包括栅极和形成在N阱中的第一和第二P +掺杂区域，其中第一P +区域电连接到相应的位线。存取PMOS包括栅极和形成在N阱内的第一和第二P +区，其中第一P +区电连接到编程/擦除PMOS的第二P +区，并且栅极电连接到相应的字线。控制栅极NMOS包括源极，漏极和栅极，其中源极和第三漏极以及p掺杂的阱电连接到相应的控制栅极线，并且栅极电连接到编程/擦除的栅极 PMOS，形成电池的浮动栅极。

7. 发明授权

US07835186B2 Method of programming a selected memory cell 有权
标题翻译：编程选定存储单元的方法
公开(公告)号：US07835186B2
公开(公告)日：2010-11-16
申请号：US12168858
申请日：2008-07-07
申请人： Nirmal Ratnakumar , Venkatraman Prabhakar , David Kuan-Yu Liu
发明人： Nirmal Ratnakumar , Venkatraman Prabhakar , David Kuan-Yu Liu
IPC分类号： G11C11/34
CPC分类号： G11C16/0441 , G11C16/3427 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell.
摘要翻译：一种包括多个存储单元的存储器件，每个存储器单元具有与编程/擦除PMOS晶体管共享浮置栅极的控制栅极NMOS晶体管，该晶体管又与访问PMOS晶体管串联连接。存储单元形成在形成在P基板中的公共N阱中，NMOS晶体管形成在p掺杂的凹穴或基底中。编程/擦除PMOS包括栅极和形成在N阱中的第一和第二P +掺杂区域，其中第一P +区域电连接到相应的位线。存取PMOS包括栅极和形成在N阱内的第一和第二P +区，其中第一P +区电连接到编程/擦除PMOS的第二P +区，并且栅极电连接到相应的字线。控制栅极NMOS包括源极，漏极和栅极，其中源极和第三漏极以及p掺杂的阱电连接到相应的控制栅极线，并且栅极电连接到编程/擦除的栅极 PMOS，形成电池的浮动栅极。

8. 发明授权

US07835184B2 EEPROM memory cell with first-dopant-type control gate transister, and second-dopant type program/erase and access transistors formed in common well 有权
标题翻译：具有第一掺杂剂型控制栅极转移器的EEPROM存储器单元，以及形成在共同阱中的第二掺杂型编程/擦除和存取晶体管
公开(公告)号：US07835184B2
公开(公告)日：2010-11-16
申请号：US12233294
申请日：2008-09-18
申请人： Nirmal Ratnakumar , Venkatraman Prabhakar , David Kuan-Yu Liu
发明人： Nirmal Ratnakumar , Venkatraman Prabhakar , David Kuan-Yu Liu
IPC分类号： G11C11/34
CPC分类号： G11C16/0441 , G11C16/3427 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell.
摘要翻译：一种包括多个存储单元的存储器件，每个存储器单元具有与编程/擦除PMOS晶体管共享浮置栅极的控制栅极NMOS晶体管，该晶体管又与访问PMOS晶体管串联连接。存储单元形成在形成在P基板中的公共N阱中，NMOS晶体管形成在p掺杂的凹穴或基底中。编程/擦除PMOS包括栅极和形成在N阱中的第一和第二P +掺杂区域，其中第一P +区域电连接到相应的位线。存取PMOS包括栅极和形成在N阱内的第一和第二P +区，其中第一P +区电连接到编程/擦除PMOS的第二P +区，栅极电连接到相应的字线。控制栅极NMOS包括源极，漏极和栅极，其中源极和第三漏极以及p掺杂的阱电连接到相应的控制栅极线，并且栅极电连接到编程/擦除的栅极 PMOS，形成电池的浮动栅极。

9. 发明授权

US07791955B2 Method of erasing a block of memory cells 有权
标题翻译：擦除存储单元块的方法
公开(公告)号：US07791955B2
公开(公告)日：2010-09-07
申请号：US12168863
申请日：2008-07-07
申请人： Nirmal Ratnakumar , Venkatraman Prabhakar , David Kuan-Yu Liu
发明人： Nirmal Ratnakumar , Venkatraman Prabhakar , David Kuan-Yu Liu
IPC分类号： G11C11/34
CPC分类号： G11C16/0441 , G11C16/3427 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell.
摘要翻译：一种包括多个存储单元的存储器件，每个存储器单元具有与编程/擦除PMOS晶体管共享浮置栅极的控制栅极NMOS晶体管，该晶体管又与访问PMOS晶体管串联连接。存储单元形成在形成在P基板中的公共N阱中，NMOS晶体管形成在p掺杂的凹穴或基底中。编程/擦除PMOS包括栅极和形成在N阱中的第一和第二P +掺杂区域，其中第一P +区域电连接到相应的位线。存取PMOS包括栅极和形成在N阱内的第一和第二P +区，其中第一P +区电连接到编程/擦除PMOS的第二P +区，栅极电连接到相应的字线。控制栅极NMOS包括源极，漏极和栅极，其中源极和第三漏极以及p掺杂的阱电连接到相应的控制栅极线，并且栅极电连接到编程/擦除的栅极 PMOS，形成电池的浮动栅极。

10. 发明申请

US20080225601A1 EEPROM MEMORY DEVICE WITH CELL HAVING NMOS IN A P POCKET AS A CONTROL GATE, PMOS PROGRAM/ERASE TRANSISTOR, AND PMOS ACCESS TRANSISTOR IN A COMMON WELL 有权
标题翻译：具有作为控制门，PMOS程序/擦除晶体管和PMOS访问晶体管的P端口中的NMOS的单元的EEPROM存储器件
公开(公告)号：US20080225601A1
公开(公告)日：2008-09-18
申请号：US11685111
申请日：2007-03-12
申请人： Nirmal Ratnakumar , Venkatraman Prabhakar , David Kuan-Yu Liu
发明人： Nirmal Ratnakumar , Venkatraman Prabhakar , David Kuan-Yu Liu
IPC分类号： G11C16/04
CPC分类号： G11C16/0441 , G11C16/3427 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell.
摘要翻译：一种包括多个存储单元的存储器件，每个存储器单元具有与编程/擦除PMOS晶体管共享浮置栅极的控制栅极NMOS晶体管，该晶体管又与访问PMOS晶体管串联连接。存储单元形成在形成在P基板中的公共N阱中，NMOS晶体管形成在p掺杂的凹穴或基底中。编程/擦除PMOS包括栅极和形成在N阱中的第一和第二P +掺杂区域，其中第一P +区域电连接到相应的位线。存取PMOS包括栅极和形成在N阱内的第一和第二P +区，其中第一P +区电连接到编程/擦除PMOS的第二P +区，栅极电连接到相应的字线。控制栅极NMOS包括源极，漏极和栅极，其中源极和第三漏极以及p掺杂的阱电连接到相应的控制栅极线，并且栅极电连接到编程/擦除的栅极 PMOS，形成电池的浮动栅极。

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