专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US5828131A Low temperature formation of low resistivity titanium silicide 失效
标题翻译：低电阻率硅化钛的低温形成
公开(公告)号：US5828131A
公开(公告)日：1998-10-27
申请号：US586046
申请日：1996-01-16
申请人： Cyril Cabral, Jr. , Lawrence Alfred Clevenger , Francois Max d'Heurle , James McKell Edwin Harper , Randy William Mann , Glen Lester Miles , James Spiros Nakos , Ronnen Andrew Roy , Katherine L. Saenger
发明人： Cyril Cabral, Jr. , Lawrence Alfred Clevenger , Francois Max d'Heurle , James McKell Edwin Harper , Randy William Mann , Glen Lester Miles , James Spiros Nakos , Ronnen Andrew Roy , Katherine L. Saenger
IPC分类号： C23C20/02 , C30B1/02 , H01L21/28 , H01L21/285 , H01L21/336 , H01L29/45
CPC分类号： C30B1/02 , C30B29/10 , H01L21/28518 , H01L29/665
摘要： Low resistivity titanium silicide, and semiconductor devices incorporating the same, may be formed by titanium alloy comprising titanium and 1-20 atomic percent refractory metal deposited in a layer overlying a silicon substrate, the substrate is then heated to a temperature sufficient to substantially form C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, and more preferably is Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900.degree. C., and more preferably between about 600.degree.-700.degree. C.
摘要翻译：低电阻率钛硅化物和包含该低电阻率钛硅化物的半导体器件可以由在钛硅衬底上沉积的钛和1-20原子百分比的难熔金属的钛合金形成，然后将衬底加热至足以基本形成C54 相钛硅化物。钛合金还可以包含硅，难熔金属可以是Mo，W，Ta，Nb，V或Cr，更优选是Ta或Nb。用于形成低电阻率硅化钛的加热步骤在低于900℃的温度下进行，更优选在约600℃至700℃之间。

82. 发明授权

US5585998A Isolated sidewall capacitor with dual dielectric 失效
标题翻译：隔离侧壁电容器，双电介质
公开(公告)号：US5585998A
公开(公告)日：1996-12-17
申请号：US577166
申请日：1995-12-22
申请人： David E. Kotecki , William H. Ma , Katherine L. Saenger
发明人： David E. Kotecki , William H. Ma , Katherine L. Saenger
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/115 , H01G4/06 , H01G4/008 , H01G7/00
CPC分类号： H01L27/11502 , H01L27/10852 , H01L28/55 , Y10T29/435
摘要： An isolated sidewall capacitor with dual dielectric, which includes two capacitors. The first capacitor includes a first conductor on top of a substrate, a first non-conductor on top of and substantially in register with the first conductor, the first conductor and first non-conductor having a first opening formed therein, a non-conductive sidewall spacer formed in the first opening, the non-conductive sidewall spacer having a second opening formed therein, and a second conductor formed in the second opening. The second capacitor includes the second conductor, a first non-conductor disposed over the top portion of the second conductor, a third conductor disposed over the first non-conductor, and the third conductor electrically connected to the first conductor. A second non-conductor isolates the first conductor from the second conductor.
摘要翻译：具有双电介质的隔离侧壁电容器，其包括两个电容器。所述第一电容器包括位于衬底顶部的第一导体，位于所述第一导体顶部并基本上与所述第一导体对准的第一非导体，所述第一导体和第一非导体具有形成在其中的第一开口，非导电侧壁在第一开口中形成的间隔件，其中形成有第二开口的非导电侧壁隔离件和形成在第二开口中的第二导体。第二电容器包括第二导体，设置在第二导体的顶部上的第一非导体，设置在第一非导体上的第三导体，以及电连接到第一导体的第三导体。第二非导体将第一导体与第二导体隔离。

83. 发明申请

US20120068267A1 STRAINED DEVICES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES 有权
公开(公告)号：US20120068267A1
公开(公告)日：2012-03-22
申请号：US12886881
申请日：2010-09-21
申请人： Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Katherine L. Saenger
发明人： Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Katherine L. Saenger
IPC分类号： H01L29/786 , H01L21/762
CPC分类号： H01L21/84 , H01L21/823807
摘要： Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe.

84. 发明申请

US20110086473A1 HYBRID ORIENTATION SEMICONDUCTOR STRUCTURE WITH REDUCED BOUNDARY DEFECTS AND METHOD OF FORMING SAME 有权
标题翻译：具有减少边界缺陷的混合方向半导体结构及其形成方法
公开(公告)号：US20110086473A1
公开(公告)日：2011-04-14
申请号：US12972771
申请日：2010-12-20
申请人： Haizhou Yin , John A. Ott , Katherine L. Saenger , Chun-Yung Sung
发明人： Haizhou Yin , John A. Ott , Katherine L. Saenger , Chun-Yung Sung
IPC分类号： H01L21/8238 , H01L21/265
CPC分类号： H01L21/02694 , H01L21/02532 , H01L21/76264 , Y10S438/973
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for forming hybrid orientation substrates and semiconductor device structures. A direct-silicon-bonded (DSB) silicon layer having a (011) surface crystal orientation is bonded to a base silicon substrate having a (001) surface crystal orientation to form a DSB wafer in which the in-plane direction of the (011) DSB layer is aligned with an in-plane direction of the (001) base substrate. Selected regions of the DSB layer are amorphized down to the base substrate to form amorphized regions aligned with the mutually orthogonal in-plane directions of the (001) base substrate, followed by recrystallization using the base substrate as a template. This optimal arrangement of DSB layer, base substrate, and amorphized region orientation provides a near-vertical, essentially defect-free boundary between original-orientation and changed-orientation silicon regions, thus enabling complete boundary region removal with smaller footprint shallow trench isolation than possible with ATR methods not so optimized.
摘要翻译：本发明提供用于形成混合取向基板和半导体器件结构的改进的非晶化/模板重结晶（ATR）方法。具有（011）表面晶体取向的直接硅键合（DSB）硅层被结合到具有（001）表面晶体取向的基底硅基板上，以形成其中面内<110>方向的DSB晶片（011）DSB层与（001）基底的面内<110>方向对准。 DSB层的选定区域被非晶化到底部基板以形成与（001）基底基板的相互正交的平面内100°方向对准的非晶形区域，然后使用基底基板作为模板进行重结晶。 DSB层，基底和非晶区域取向的这种最佳布置提供了原始取向和改变取向硅区域之间近似垂直的，基本上无缺陷的边界，因此可以实现完整的边界区域移除，并且可以实现更小的占地面积的浅沟槽隔离 ATR方法没有如此优化。

85. 发明申请

US20100044758A1 CMOS WITH CHANNEL P-FINFET AND CHANNEL N-FINFET HAVING DIFFERENT CRYSTALLINE ORIENTATIONS AND PARALLEL FINS 有权
标题翻译：具有通道的具有不同晶体结构和并联FINS的通道P-FINFET和通道N-FinFET的CMOS
公开(公告)号：US20100044758A1
公开(公告)日：2010-02-25
申请号：US12197459
申请日：2008-08-25
申请人： GUY M. COHEN , Katherine L. Saenger
发明人： GUY M. COHEN , Katherine L. Saenger
IPC分类号： H01L29/04 , H01L21/84 , G06F19/00
CPC分类号： H01L27/0924 , H01L21/34 , H01L21/845 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/045 , H01L29/66795 , H01L29/785
摘要： An integrated circuit is fabricated with at least one p-FinFET device and at least one n-FinFET device situated parallel to each other. A first silicon layer having a first crystalline orientation is bonded to a second silicon layer having a second crystalline orientation. The first and second orientations are different from each other. A volume of material is formed that extends through the first layer from the second layer up to the surface of the first layer. The material has a crystalline orientation that substantially matches the orientation of the second layer. Areas of the surface of the first layer that are outside of the region are selectively etched to create a first plurality of fins and areas inside the region to create a second plurality of fins. The etching leaves the first and second pluralities of fins parallel to each other with different surface crystal orientations.
摘要翻译：制造具有至少一个p-FinFET器件和至少一个彼此平行的n-FinFET器件的集成电路。具有第一晶体取向的第一硅层被结合到具有第二晶体取向的第二硅层上。第一和第二取向彼此不同。形成一定体积的材料，其从第二层延伸穿过第一层直到第一层的表面。该材料具有基本上与第二层的取向一致的晶体取向。选择性地蚀刻在区域外部的第一层的表面的区域，以在该区域内产生第一多个散热片和区域，以产生第二多个散热片。蚀刻使得第一和第二多个翅片彼此平行但具有不同的表面晶体取向。

86. 发明申请

US20100006850A1 BEOL COMPATIBLE FET STRUCTURE 有权
标题翻译： BEOL兼容FET结构
公开(公告)号：US20100006850A1
公开(公告)日：2010-01-14
申请号：US12561827
申请日：2009-09-17
申请人： Christy S. Tyberg , Katherine L. Saenger , Jack O. Chu , Harold J. Hovel , Robert L. Wisnieff , Kerry Bernstein , Stephen W. Bedell
发明人： Christy S. Tyberg , Katherine L. Saenger , Jack O. Chu , Harold J. Hovel , Robert L. Wisnieff , Kerry Bernstein , Stephen W. Bedell
IPC分类号： H01L23/522 , H01L29/786 , H01L29/04
CPC分类号： H01L23/5226 , H01L23/53271 , H01L27/124 , H01L27/1248 , H01L2924/0002 , H01L2924/00
摘要： This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.
摘要翻译：本发明提供了用于在线路后端（BEOL）互连结构中并入薄膜晶体管的结构和制造工艺。所描述的结构和制造工艺与BEOL互连结构的处理要求相兼容。结构和制造工艺利用已经并入到互连布线层中的现有处理步骤和材料，以便降低与在这些层级中引入薄膜晶体管相关联的附加成本。与现有技术的3D集成方法相比，该结构能够实现多层次的垂直（3D）集成，具有改进的可制造性和可靠性。

87. 发明申请

US20080248626A1 SHALLOW TRENCH ISOLATION SELF-ALIGNED TO TEMPLATED RECRYSTALLIZATION BOUNDARY 审中-公开
标题翻译： SHOWOW TRENCH ISOLATION自对准至模拟重构边界
公开(公告)号：US20080248626A1
公开(公告)日：2008-10-09
申请号：US11697102
申请日：2007-04-05
申请人： Yaocheng Liu , Zhijiong Luo , Katherine L. Saenger , Chun-Yung Sung , Rajasekhar Venigalla , Haizhou Yin
发明人： Yaocheng Liu , Zhijiong Luo , Katherine L. Saenger , Chun-Yung Sung , Rajasekhar Venigalla , Haizhou Yin
IPC分类号： H01L21/762
CPC分类号： H01L21/26506 , H01L21/02667 , H01L21/187 , H01L21/76224
摘要： A hybrid orientation direct-semiconductor-bond (DSB) substrate with shallow trench isolation (STI) that is self-aligned to recrystallization boundaries is formed by patterning a hard mask layer for STI, a first amorphization implantation into openings in the hard mask layer, lithographic patterning of portions of a top semiconductor layer, a second amorphization implantation into exposed portions of the DSB substrate, recrystallization of the portions of the top semiconductor layer, and formation of STI utilizing the pattern in the hard mask layer. The edges of patterned photoresist for the second amorphization implantation are located within the openings in the patterned hard mask layer. Defective boundary regions formed underneath the openings in the hard mask layer are removed during the formation of STI to provide a leakage path free substrate. Due to elimination of a requirement for increased STI width, device density is increased compared to non-self-aligning process integration schemes.
摘要翻译：通过将STI的硬掩模层图案化，在硬掩模层的开口中进行第一非晶化注入，形成具有与重结晶边界自对准的浅沟槽隔离（STI）的混合取向直接半导体结合（DSB）顶部半导体层的部分的平版印刷图案化，第二非晶化注入到DSB衬底的暴露部分中，顶部半导体层的部分的再结晶，以及利用硬掩模层中的图案形成STI。用于第二非晶化注入的图案化光致抗蚀剂的边缘位于图案化的硬掩模层的开口内。在形成STI期间去除在硬掩模层中形成在开口下面的有缺陷的边界区域，以提供无泄漏路径的衬底。由于消除了对于增加的STI宽度的要求，与非自对准工艺集成方案相比，器件密度增加。

88. 发明申请

US20080142894A1 GATE STACK ENGINEERING BY ELECTROCHEMICAL PROCESSING UTILIZING THROUGH-GATE-DIELECTRIC CURRENT FLOW 有权
标题翻译：通过电化学处理利用栅极电介质电流流动的栅极堆叠工程
公开(公告)号：US20080142894A1
公开(公告)日：2008-06-19
申请号：US12040350
申请日：2008-02-29
申请人： Philippe M. Vereecken , Veeraraghavan S. Basker , Cyril Cabral , Emanuel I. Cooper , Hariklia Deligianni , Martin M. Frank , Rajarao Jammy , Vamsi Krishna Paruchuri , Katherine L. Saenger , Xiaoyan Shao
发明人： Philippe M. Vereecken , Veeraraghavan S. Basker , Cyril Cabral , Emanuel I. Cooper , Hariklia Deligianni , Martin M. Frank , Rajarao Jammy , Vamsi Krishna Paruchuri , Katherine L. Saenger , Xiaoyan Shao
IPC分类号： H01L27/088 , H01L29/423
CPC分类号： H01L21/2885 , C25D3/50 , C25D5/02 , C25D5/024 , C25D5/54 , C25D7/123 , C25D9/04 , C25F3/14 , H01L21/28079 , H01L21/28114 , H01L21/76885 , H01L29/513 , H01L29/517 , H01L29/78648
摘要： A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.
摘要翻译：提供了一种用于将栅极金属或其它导电或半导体材料直接电镀在诸如栅极电介质的电介质上的方法。该方法包括选择衬底，电介质层和电解质溶液或熔体，其中衬底，电介质层和电解质溶液或熔体的组合允许电化学电流从衬底通过电介质层进入电解质溶液或熔化。还提供了利用电介质电流流动的电介质电化学修饰方法。

89. 发明授权

US07064064B2 Copper recess process with application to selective capping and electroless plating 有权
标题翻译：铜凹槽工艺，适用于选择性封盖和无电镀
公开(公告)号：US07064064B2
公开(公告)日：2006-06-20
申请号：US11058783
申请日：2005-02-16
申请人： Shyng-Tsong Chen , Timothy J. Dalton , Kenneth M. Davis , Chao-Kun Hu , Fen F. Jamin , Steffen K. Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael F. Lofaro , Sandra G. Malhotra , Chandrasekhar Narayan , David L. Rath , Judith M. Rubino , Katherine L. Saenger , Andrew H. Simon , Sean P. E. Smith , Wei-tsu Tseng
发明人： Shyng-Tsong Chen , Timothy J. Dalton , Kenneth M. Davis , Chao-Kun Hu , Fen F. Jamin , Steffen K. Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael F. Lofaro , Sandra G. Malhotra , Chandrasekhar Narayan , David L. Rath , Judith M. Rubino , Katherine L. Saenger , Andrew H. Simon , Sean P. E. Smith , Wei-tsu Tseng
IPC分类号： H01L21/44
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/76847 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.
摘要翻译：公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。

90. 发明授权

US5633781A Isolated sidewall capacitor having a compound plate electrode 失效
标题翻译：具有复合板电极的隔离侧壁电容器
公开(公告)号：US5633781A
公开(公告)日：1997-05-27
申请号：US577168
申请日：1995-12-22
申请人： Katherine L. Saenger , David E. Kotecki
发明人： Katherine L. Saenger , David E. Kotecki
IPC分类号： H01L21/02 , H01L21/8242 , H01K1/16
CPC分类号： H01L27/1085 , H01L27/10852 , H01L28/40
摘要： A capacitor structure is provided, with a first conductor on top of a substrate having at least one layer of dielectric material thereon; a first non-conductor on top of and substantially in register with the first conductor, the first conductor and first non-conductor having a first opening formed therein; a second conductor, in electrical contact with the first conductor, formed on the sidewalls of the first opening; a non-conductive sidewall spacer formed in the first opening and contacting the second conductor, the non-conductive sidewall spacer having a second opening formed therein; and a third conductor formed in the second opening.
摘要翻译：提供一种电容器结构，其中第一导体位于衬底的顶部，其上具有至少一层电介质材料; 在第一导体顶部并基本上与第一导体对准的第一非导体，第一导体和第一非导体具有形成在其中的第一开口; 与第一导体电接触的第二导体，形成在第一开口的侧壁上; 形成在所述第一开口中并接触所述第二导体的非导电侧壁间隔物，所述非导电侧壁间隔件具有形成在其中的第二开口; 以及形成在第二开口中的第三导体。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式