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1. 发明授权

US08729549B2 Test structure and methodology for three-dimensional semiconductor structures 有权
标题翻译：三维半导体结构的测试结构和方法
公开(公告)号：US08729549B2
公开(公告)日：2014-05-20
申请号：US13533191
申请日：2012-06-26
申请人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
发明人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
IPC分类号： H01L23/58
CPC分类号： H01L22/32 , H01L21/4846 , H01L21/6835 , H01L21/76898 , H01L23/49827 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2221/6835 , H01L2224/13005 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079
摘要： A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.
摘要翻译：在外围测试结构衬底内形成通孔的多个外围测试结构衬底（PTSS）。周边测试结构层和至少一个功能层通过通孔形成在多个PTSS的一侧上。多个PTSS通孔中的另一侧在外围测试结构层和至少一个功能层的制造过程中暴露出来，以提供用于在整个制造顺序中测试各个层的功能性的接入点。可以在完成所有至少一个功能层的所有制造之后执行C4键合。不需要3D组装载体或C4载体衬底，因为外围测试结构衬底具有足够的机械强度以支撑外围测试结构层和至少一个功能层。

2. 发明申请

US20140043757A1 ELECTRO-RHEOLOGICAL MICRO-CHANNEL ANISOTROPIC COOLED INTEGRATED CIRCUITS AND METHODS THEREOF 有权
标题翻译：电 - 流变微通道各向异性冷却集成电路及其方法
公开(公告)号：US20140043757A1
公开(公告)日：2014-02-13
申请号：US13568248
申请日：2012-08-07
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie
IPC分类号： G05D23/00 , H05K7/20
CPC分类号： G05D23/1919 , G06F1/206 , H01L23/38 , H01L23/473 , H01L2224/16225 , H01L2924/1305 , H01L2924/15174 , H01L2924/15311 , H05K7/20272 , H05K7/20281 , H05K7/20518 , H01L2924/00
摘要： An integrated circuit chip having micro-channels formed in multiple regions of the integrated circuit chip and a method of cooling the integrated circuit chip. The method includes for any region of the multiple regions, allowing a coolant to flow through micro-channels of the region only when a temperature of the region exceed a first specified temperature and blocking the coolant from flowing through the micro-channels of the region when a temperature of the region is below a second specified temperature.
摘要翻译：具有形成在集成电路芯片的多个区域中的微通道的集成电路芯片和冷却集成电路芯片的方法。该方法包括对于多个区域的任何区域，只有当该区域的温度超过第一规定温度并且阻止冷却剂流过该区域的微通道时，冷却剂才能流过该区域的微通道，该区域的温度低于第二规定温度。

3. 发明授权

US08575964B2 Inactivity triggered self clocking logic family 有权
标题翻译：不活动触发自我计时逻辑家族
公开(公告)号：US08575964B2
公开(公告)日：2013-11-05
申请号：US13426776
申请日：2012-03-22
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , John Sargis, Jr. , Sebastian T. Ventrone , Charles S. Woodruff
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , John Sargis, Jr. , Sebastian T. Ventrone , Charles S. Woodruff
IPC分类号： H03K19/00
CPC分类号： H03K19/0966 , H03K19/0013
摘要： Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure.
摘要翻译：电路的局部逻辑区域包括电连接到局部电阻电压电路的本地比较器，局部电阻接地电路和局部寄存器结构。当本地参考电压低于本地电压阈值时，本地比较器会向本地寄存器结构提供时钟脉冲。本地组合逻辑结构中的活动导致本地参考电压低于局部参考电压，而与全局参考电压的变化无关，导致比较器输出时钟脉冲（具有足够的延迟以允许逻辑结果存储在寄存器中只有在本地逻辑设备中已经满足设置时间之后）。这消除了对时钟分配树的需要，从而在局部组合逻辑结构中没有活动时节省功率。

4. 发明授权

US08343814B2 Compact multi-port cam cell implemented in 3D vertical integration 有权
标题翻译：紧凑型多端口凸轮单元，实现3D垂直整合
公开(公告)号：US08343814B2
公开(公告)日：2013-01-01
申请号：US12542235
申请日：2009-08-17
申请人： Robert J. Bucki , Jagreet S. Atwal , Joseph S. Barnes , Kerry Bernstein , Eric Robinson
发明人： Robert J. Bucki , Jagreet S. Atwal , Joseph S. Barnes , Kerry Bernstein , Eric Robinson
IPC分类号： H01L21/335
CPC分类号： H01L25/0657 , G11C15/00 , H01L21/6835 , H01L24/24 , H01L24/82 , H01L25/50 , H01L27/0688 , H01L27/1203 , H01L2221/68368 , H01L2224/24226 , H01L2224/80896 , H01L2224/83894 , H01L2224/9202 , H01L2224/9212 , H01L2225/06513 , H01L2225/06541 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/04953 , H01L2924/10329 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： A multi-ported CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-ported CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the multi-port CAM can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-port CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays. Each compare match line and data bit line has the length associated with a simple two-dimensional Static Random Access Memory (SRAM) cell array.
摘要翻译：提供了一种多移动CAM单元，其中增加行程距离的负面影响已经大大减少。多端口CAM单元在本发明中是通过利用三维积分来实现的，其中多个有源电路层是垂直堆叠的，并且使用垂直排列的互连将器件从堆叠层之一连接到另一层叠层中的另一个器件。通过垂直堆叠具有垂直排列的互连的多个有源电路层，多端口CAM的每个比较端口可以在主数据存储单元上方或下方的单独层上实现。这允许在与标准随机存取存储器（RAM）单元相同的区域覆盖范围内实现多端口CAM结构，使数据访问最小化并匹配比较延迟。每个比较匹配线和数据位线具有与简单的二维静态随机存取存储器（SRAM）单元阵列相关联的长度。

5. 发明申请

US20120326333A1 SEMICONDUCTOR CHIP STACKING FOR REDUNDANCY AND YIELD IMPROVEMENT 有权
标题翻译：用于冗余和改进的半导体芯片堆叠
公开(公告)号：US20120326333A1
公开(公告)日：2012-12-27
申请号：US13607680
申请日：2012-09-08
申请人： Kerry Bernstein , Philip G. Emma , Michael Ignatowski
发明人： Kerry Bernstein , Philip G. Emma , Michael Ignatowski
IPC分类号： H01L25/00
CPC分类号： H01L25/0657 , H01L25/0652 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A stacked semiconductor chip comprising multiple unit chips contains multiple instances of a first chip component that have a low yield and are distributed among the multiple unit chips. An instance of the first chip component within a first unit chip is logically paired with at least another instance of the first chip component within at least another unit chip so that the combination of the multiple instances of the first chip component across the multiple unit chips constitute a functional block providing the functionality of a fully functional instance of the first chip component. The stacked semiconductor chip may include multiple instances of a second chip component having a high yield and distributed across the multiple unit chips. Multiple low yield components constitute a functional block providing an enhanced overall yield, while high yield components are utilized to their full potential functionality.
摘要翻译：包括多个单元芯片的堆叠半导体芯片包含具有低产出并分布在多个单元芯片之间的第一芯片组件的多个实例。第一单元芯片内的第一芯片组件的实例与至少另一个单元芯片内的第一芯片组件的至少另一个实例进行逻辑配对，使得跨多个单元芯片的第一芯片组件的多个实例的组合构成提供第一芯片组件的完全功能实例的功能的功能块。层叠的半导体芯片可以包括具有高产量并分布在多个单元芯片上的第二芯片组件的多个实例。多个低产量组分构成提供增强的总收率的功能块，而高产量组分被用于其全部潜在功能。

6. 发明授权

US08263472B2 Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices 失效
标题翻译：用于绝缘体上硅（SOI）器件的深沟槽静电放电（ESD）保护二极管
公开(公告)号：US08263472B2
公开(公告)日：2012-09-11
申请号：US13324486
申请日：2011-12-13
申请人： John E. Barth, Jr. , Kerry Bernstein
发明人： John E. Barth, Jr. , Kerry Bernstein
IPC分类号： H01L21/76
CPC分类号： H01L29/861 , H01L21/761 , H01L21/76264 , H01L23/535 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.
摘要翻译：半导体包括第一极性类型的体基板，设置在体基板上的掩埋绝缘体层，设置在包括浅沟槽隔离区域和第一极性类型的扩散区域的掩埋绝缘体层的顶部上的有源半导体层，第二极性类型的带区域直接设置在掩埋绝缘体层的正下方并形成导电路径，第二极性类型的阱区域布置在本体衬底中并与带区域接触，填充有导电材料的深沟槽设置在阱区内的第一极性类型和由深沟槽的下部与阱区之间的接合部限定的静电放电（ESD）保护二极管。

7. 发明授权

US08234554B2 Soft error correction in sleeping processors 有权
标题翻译：睡眠处理器中的软错误校正
公开(公告)号：US08234554B2
公开(公告)日：2012-07-31
申请号：US12170462
申请日：2008-07-10
申请人： Kerry Bernstein , Norman J. Rohrer
发明人： Kerry Bernstein , Norman J. Rohrer
IPC分类号： H03M13/00
CPC分类号： H03M13/15 , G06F11/1008 , H03M13/098 , H03M13/13 , H03M13/1505 , H03M13/19
摘要： An error-correction code is generated on a line-by-line basis of the physical logic register and latch contents that store encoded words within a processor just before the processor is put into sleep mode, and later-generated syndrome bits are checked for any soft errors when the processor wakes back up, e.g., as part of the power-up sequence.
摘要翻译：在处理器进入睡眠模式之前，将物理逻辑寄存器和锁存内容逐行生成在处理器内的处理器内，生成错误校正码，并检查后来生成的校验码位处理器唤醒时出现软错误，例如作为上电顺序的一部分。

8. 发明申请

US20120066657A1 METHOD OF DESIGNING AN INTEGRATED CIRCUIT BASED ON A COMBINATION OF MANUFACTURABILITY, TEST COVERAGE AND, OPTIONALLY, DIAGNOSTIC COVERAGE 有权
标题翻译：基于可制造性，测试覆盖和可选择的诊断覆盖的组合设计集成电路的方法
公开(公告)号：US20120066657A1
公开(公告)日：2012-03-15
申请号：US12880228
申请日：2010-09-13
申请人： Kerry Bernstein , James A. Culp , Leah M.P. Pastel , Kirk D. Peterson , Norman J. Rohrer
发明人： Kerry Bernstein , James A. Culp , Leah M.P. Pastel , Kirk D. Peterson , Norman J. Rohrer
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5045 , G06F2217/12 , Y02P90/265
摘要： Disclose are embodiments of an integrated circuit design method based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage. Design-for manufacturability (DFM) modifications to the layout of an integrated circuit can be made in light of test coverage. Alternatively, test coverage of an integrated circuit can be established in light of DFM modifications. Alternatively, an iterative process can be performed, where DFM modifications to the layout of an integrated circuit are made in light of test coverage and then test coverage is altered in light of the DFM modifications. Alternatively, DFM modifications to the layout of an integrated circuit can be made in light of test coverage and also diagnostic coverage. In any case, after making DFM modifications and establishing test coverage, any unmodified and untested nodes (and, optionally, any unmodified and undiagnosable tested nodes) in the integrated circuit can be identified and tagged for subsequent in-line inspection.
摘要翻译：披露是基于可制造性，测试覆盖和任选的诊断覆盖的组合的集成电路设计方法的实施例。根据测试覆盖范围，可以对集成电路布局的可制造性（DFM）进行设计修改。或者，可以根据DFM修改建立集成电路的测试覆盖。或者，可以执行迭代处理，其中根据测试覆盖进行DFM对集成电路的布局的修改，然后根据DFM修改来改变测试覆盖。或者，DFM可以根据测试覆盖范围和诊断覆盖范围对集成电路布局进行修改。在任何情况下，在进行DFM修改和建立测试覆盖之后，可以识别和标记集成电路中的任何未修改和未测试的节点（以及可选地，任何未修改和不可判定的测试节点）以便随后的在线检查。

9. 发明授权

US08097525B2 Vertical through-silicon via for a semiconductor structure 有权
标题翻译：用于半导体结构的垂直通硅硅通孔
公开(公告)号：US08097525B2
公开(公告)日：2012-01-17
申请号：US12201580
申请日：2008-08-29
申请人： John E. Barth, Jr. , Kerry Bernstein
发明人： John E. Barth, Jr. , Kerry Bernstein
IPC分类号： H01L21/00
CPC分类号： H01L23/481 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor structure includes at least one silicon substrate having first and second planar surfaces, and at least one through silicon via filled with a conductive material and extending vertically through the first planar surface of the at least one silicon substrate to the second planar surface thereof. The through silicon via forms a vertical interconnection between a plurality of electronic circuits and an amount of dielectric insulation surrounding the through silicon via is varied based on a defined function of the through silicon via.
摘要翻译：半导体结构包括具有第一和第二平面表面的至少一个硅衬底，以及填充有导电材料并且至少穿过至少一个硅衬底的第一平坦表面垂直延伸到其第二平坦表面的至少一个穿硅通孔。穿通硅通孔在多个电子电路之间形成垂直互连，并且围绕穿过硅通孔的绝缘绝缘体的量基于硅通孔的限定功能而变化。

10. 发明授权

US08013342B2 Double-sided integrated circuit chips 有权
标题翻译：双面集成电路芯片
公开(公告)号：US08013342B2
公开(公告)日：2011-09-06
申请号：US11939612
申请日：2007-11-14
申请人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
IPC分类号： H01L29/04
CPC分类号： G06F17/5077 , H01L21/6835 , H01L21/76895 , H01L21/84 , H01L23/481 , H01L23/535 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L29/045 , H01L2221/6835 , H01L2221/68359 , H01L2221/68368 , H01L2224/83894 , H01L2224/9202 , H01L2225/06513 , H01L2924/01019 , H01L2924/01029 , H01L2924/0132 , H01L2924/1305 , H01L2924/14 , H01L2924/19041 , H01L2924/01007 , H01L2924/01022 , H01L2924/00
摘要： A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
摘要翻译：双面集成电路芯片，制造双面集成电路芯片的方法和双面集成电路芯片的设计结构。该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。下晶片可以包括布线水平。下部晶片可以包括用于触点的着陆焊盘。与下晶片的硅层的接触可以被硅化。

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