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1. 发明授权

US08890112B2 Controlling ferroelectricity in dielectric films by process induced uniaxial strain 有权
标题翻译：通过工艺诱导的单轴应变控制电介质薄膜的铁电性
公开(公告)号：US08890112B2
公开(公告)日：2014-11-18
申请号：US13557385
申请日：2012-07-25
申请人： Catherine A. Dubourdieu , Martin M. Frank
发明人： Catherine A. Dubourdieu , Martin M. Frank
IPC分类号： H01L21/02 , H01L29/66 , H01L49/02 , H01L29/78 , H01L21/28
CPC分类号： H01L21/28291 , H01L28/55 , H01L29/66636 , H01L29/6684 , H01L29/7804 , H01L29/78391 , H01L29/7843 , H01L29/7848
摘要： A method of controlling ferroelectric characteristics of integrated circuit device components includes forming a ferroelectrically controllable dielectric layer over a substrate; and forming a stress exerting structure proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer by the stress exerting structure; wherein the ferroelectrically controllable dielectric layer comprises one or more of: a ferroelectric oxide layer and a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress.
摘要翻译：控制集成电路器件部件的铁电特性的方法包括在衬底上形成铁电可控的电介质层; 以及在所述铁电可控电介质层附近形成应力施加结构，使得通过所述应力施加结构在所述铁电可控电介质层中诱发基本上单轴应变; 其中所述铁电可控介电层包括以下中的一种或多种：在没有施加应力的情况下不表现出铁电性能的铁电氧化物层和正常非铁电材料层。

2. 发明授权

US08836037B2 Structure and method to form input/output devices 有权
标题翻译：结构和方法来形成输入/输出设备
公开(公告)号：US08836037B2
公开(公告)日：2014-09-16
申请号：US13584156
申请日：2012-08-13
申请人： Takashi Ando , Min Dai , Martin M. Frank , Barry P. Linder , Shahab Siddiqui
发明人： Takashi Ando , Min Dai , Martin M. Frank , Barry P. Linder , Shahab Siddiqui
IPC分类号： H01L29/78 , H01L21/314 , H01L27/088
CPC分类号： H01L21/28185 , H01L21/02181 , H01L21/28202 , H01L21/823462 , H01L29/513 , H01L29/518
摘要： A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on the same chip or wafer while providing scalability of the inversion layer of the I/O and logic transistors without significantly compromising performance or bias temperature instability (BTI) parameters.
摘要翻译：有限数量的Hi-K材料的原子层沉积（ALD）循环，然后沉积层间电介质并施加另外的Hi-K材料并且可选但优选的退火提供了增加的Hi-K材料含量和增加的输入的击穿电压与输入/输出（I / O）晶体管相比，与同一芯片或晶圆上形成的逻辑晶体管相比，同时提供I / O和逻辑晶体管的反型层的可扩展性，而不会明显地影响性能或偏置温度不稳定性（BTI）参数。

3. 发明申请

US20140042546A1 STRUCTURE AND METHOD TO FORM INPUT/OUTPUT DEVICES 有权
标题翻译：用于形成输入/输出设备的结构和方法
公开(公告)号：US20140042546A1
公开(公告)日：2014-02-13
申请号：US13584156
申请日：2012-08-13
申请人： Takashi Ando , Min Dai , Martin M. Frank , Barry P. Linder , Shahab Siddiqui
发明人： Takashi Ando , Min Dai , Martin M. Frank , Barry P. Linder , Shahab Siddiqui
IPC分类号： H01L29/78 , H01L21/314 , H01L27/088
CPC分类号： H01L21/28185 , H01L21/02181 , H01L21/28202 , H01L21/823462 , H01L29/513 , H01L29/518
摘要： A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on the same chip or wafer while providing scalability of the inversion layer of the I/O and logic transistors without significantly compromising performance or bias temperature instability (BTI) parameters.
摘要翻译：有限数量的Hi-K材料的原子层沉积（ALD）循环，然后沉积层间电介质并施加另外的Hi-K材料并且可选但优选的退火提供了增加的Hi-K材料含量和增加的输入的击穿电压与输入/输出（I / O）晶体管相比，与同一芯片或晶圆上形成的逻辑晶体管相比，同时提供I / O和逻辑晶体管的反型层的可扩展性，而不会明显地影响性能或偏置温度不稳定性（BTI）参数。

4. 发明授权

US08389300B2 Controlling ferroelectricity in dielectric films by process induced uniaxial strain 有权
标题翻译：通过工艺诱导的单轴应变控制电介质薄膜的铁电性
公开(公告)号：US08389300B2
公开(公告)日：2013-03-05
申请号：US12753270
申请日：2010-04-02
申请人： Catherine A. Dubourdieu , Martin M. Frank
发明人： Catherine A. Dubourdieu , Martin M. Frank
IPC分类号： H01L21/00
CPC分类号： H01L21/28291 , H01L28/55 , H01L29/66636 , H01L29/6684 , H01L29/7804 , H01L29/78391 , H01L29/7843 , H01L29/7848
摘要： A method of controlling ferroelectric characteristics of integrated circuit device components includes forming a ferroelectrically controllable dielectric layer over a substrate; and forming a stress exerting structure proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer by the stress exerting structure; wherein the ferroelectrically controllable dielectric layer comprises one or more of: a ferroelectric oxide layer and a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress.
摘要翻译：控制集成电路器件部件的铁电特性的方法包括在衬底上形成铁电可控的电介质层; 以及在所述铁电可控电介质层附近形成应力施加结构，使得通过所述应力施加结构在所述铁电可控电介质层中诱发基本上单轴应变; 其中所述铁电可控介电层包括以下中的一种或多种：在没有施加应力的情况下不表现出铁电性能的铁电氧化物层和正常非铁电材料层。

5. 发明申请

US20130032886A1 Low Threshold Voltage And Inversion Oxide Thickness Scaling For A High-K Metal Gate P-Type MOSFET 审中-公开
标题翻译：高K金属栅P型MOSFET的低阈值电压和反转氧化层厚度缩放
公开(公告)号：US20130032886A1
公开(公告)日：2013-02-07
申请号：US13195316
申请日：2011-08-01
申请人： Takashi Ando , Changhwan Choi , Martin M. Frank , Unoh Kwon , Vijay Narayanan
发明人： Takashi Ando , Changhwan Choi , Martin M. Frank , Unoh Kwon , Vijay Narayanan
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/0922 , H01L21/823807 , H01L29/16 , H01L29/161 , H01L29/42364 , H01L29/4966 , H01L29/517
摘要： A structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in Tinv and Vt of the pFET, while scaling Tiny and maintaining Vt for the nFET, resulting in the Vt of the pFET becoming closer to the Vt of a similarly constructed nFET with scaled Tinv values.
摘要翻译：结构具有半导体衬底以及设置在衬底上的nFET和pFET。 pFET具有形成在半导体衬底的表面上或其表面上的半导体SiGe沟道区，以及覆盖沟道区的氧化物层和覆盖氧化物层的高k电介质层的栅极电介质。栅电极覆盖在栅极电介质上，并且具有邻接高k层的下金属层，邻接下金属层的清除金属层和与清除金属层邻接的上金属层。金属层清除了衬底（nFET）中的氧和与氧化物层的SiGe（pFET）界面，导致pFET的Tinv和Vt有效降低，同时缩小Tiny并维持nFET的Vt，导致Vt pFET变得更接近具有缩放Tinv值的类似构造的nFET的Vt。

6. 发明申请

US20130001668A1 FLOATING GATE DEVICE WITH OXYGEN SCAVENGING ELEMENT 审中-公开
标题翻译：浮选闸门装置与氧气扫描元件
公开(公告)号：US20130001668A1
公开(公告)日：2013-01-03
申请号：US13550102
申请日：2012-07-16
申请人： Martin M. Frank
发明人： Martin M. Frank
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L27/11521
摘要： A floating gate device is provided. A tunnel oxide layer is formed over the channel. A floating gate is formed over the tunnel oxide layer. A high-k dielectric layer is formed over the floating gate. A control gate is formed over the high-k dielectric layer. At least one of the control gate and/or the floating gate includes an oxygen scavenging element. The oxygen scavenging element is configured to decrease an oxygen density at least one of at a first interface between the control gate and the high-k dielectric layer, at a second interface between the high-k dielectric layer and the floating gate, at a third interface between the floating gate and the tunnel oxide layer, and at a fourth interface between the tunnel oxide layer and the channel responsive to annealing.
摘要翻译：提供浮动门装置。在通道上形成隧道氧化物层。在隧道氧化物层上形成浮栅。在浮栅上形成高k电介质层。在高k电介质层上形成控制栅极。控制栅极和/或浮动栅极中的至少一个包括氧气清除元件。氧清除元件被配置为在第k个高k介电层和浮动栅极之间的第二界面处，在第三个控制栅极和高k电介质层之间的第一界面处的至少一个处降低氧气密度界面在浮动栅极和隧道氧化物层之间，并且在隧道氧化物层和沟道之间的第四界面响应于退火。

7. 发明申请

US20120306019A1 FABRICATION OF DEVICES HAVING DIFFERENT INTERFACIAL OXIDE THICKNESS VIA LATERAL OXIDATION 有权
标题翻译：具有通过侧向氧化的不同界面氧化物厚度的器件的制造
公开(公告)号：US20120306019A1
公开(公告)日：2012-12-06
申请号：US13571521
申请日：2012-08-10
申请人： Jin Cai , Eduard A. Cartier , Martin M. Frank , Marwan H. Khater
发明人： Jin Cai , Eduard A. Cartier , Martin M. Frank , Marwan H. Khater
IPC分类号： H01L27/088
CPC分类号： H01L21/823468 , H01L21/28176 , H01L21/28247 , H01L21/823462 , H01L21/823857 , H01L21/823864 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6653 , H01L29/78
摘要： A semiconductor device includes a first field effect transistor (FET) and a second FET located on a substrate, the first FET comprising a first interfacial oxide layer, and the second FET comprising a second interfacial oxide layer, wherein the second interfacial oxide layer of the second FET is thicker than the first interfacial oxide layer of the first FET; and a recess located in the substrate adjacent to the second FET.
摘要翻译：半导体器件包括位于衬底上的第一场效应晶体管（FET）和第二FET，所述第一FET包括第一界面氧化物层，所述第二FET包括第二界面氧化物层，其中所述第二界面氧化物层第二FET比第一FET的第一界面氧化物层厚; 以及位于与第二FET相邻的衬底中的凹部。

8. 发明申请

US20120193716A1 HIGH-K TRANSISTORS WITH LOW THRESHOLD VOLTAGE 有权
标题翻译：具有低阈值电压的高K晶体管
公开(公告)号：US20120193716A1
公开(公告)日：2012-08-02
申请号：US13442087
申请日：2012-04-09
申请人： Martin M. Frank
发明人： Martin M. Frank
IPC分类号： H01L29/772
CPC分类号： H01L21/28247 , H01L21/2807 , H01L21/28079 , H01L21/28088 , H01L21/28176 , H01L21/3105 , H01L21/326 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： A semiconductor structure includes a high-k dielectric layer over a semiconductor substrate; and a gate layer over the high-k dielectric layer, wherein the gate layer has a negative electrical bias during anneal.
摘要翻译：半导体结构包括半导体衬底上的高k电介质层; 以及在高k电介质层上的栅极层，其中栅极层在退火期间具有负电偏压。

9. 发明申请

US20120193348A1 HIGH-K TRANSISTORS WITH LOW THRESHOLD VOLTAGE 有权
标题翻译：具有低阈值电压的高K晶体管
公开(公告)号：US20120193348A1
公开(公告)日：2012-08-02
申请号：US13442090
申请日：2012-04-09
申请人： Martin M. Frank
发明人： Martin M. Frank
IPC分类号： H05B3/02
CPC分类号： H01L21/28247 , H01L21/2807 , H01L21/28079 , H01L21/28088 , H01L21/28176 , H01L21/3105 , H01L21/326 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： An apparatus includes a wafer annealing tool and a plurality of electrodes coupled to the wafer annealing tool, wherein the electrodes are configured to be in physical contact with a wafer so that, when the wafer is annealed, a negative electrical bias is formed across one or more gate stacks of the wafer.
摘要翻译：一种设备包括晶片退火工具和耦合到晶片退火工具的多个电极，其中电极被配置为与晶片物理接触，使得当晶片退火时，负电偏压跨越一个或更多的晶片堆叠。

10. 发明申请

US20110143482A1 SUSPENDED GERMANIUM PHOTODETECTOR FOR SILICON WAVEGUIDE 有权
标题翻译：用于硅波长的停止的德国光电转换器
公开(公告)号：US20110143482A1
公开(公告)日：2011-06-16
申请号：US13005821
申请日：2011-01-13
申请人： Solomon Assefa , Jack O. Chu , Martin M. Frank , William M. Green , Young-hee Kim , George G. Totir , Joris Van Campenhout , Yurri A. Vlasov , Ying Zhang
发明人： Solomon Assefa , Jack O. Chu , Martin M. Frank , William M. Green , Young-hee Kim , George G. Totir , Joris Van Campenhout , Yurri A. Vlasov , Ying Zhang
IPC分类号： H01L31/18
CPC分类号： H01L31/1804 , B82Y20/00 , G02B6/12004 , G02B6/136 , G02B2006/12123 , H01L31/109 , H01L31/1812 , Y02E10/547 , Y02P70/521
摘要： A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized.
摘要翻译：在第一外延硅层的顶表面上外延地形成第一硅锗合金层，第二外延硅层，第二硅锗层和锗层的垂直叠层。第二外延硅层，第二硅锗层和锗层通过介电盖部分，电介质间隔物和第一硅锗层被图案化和封装。在第一和第二硅层之间去除硅锗层以形成硅锗台面结构，其结构上支撑包括硅部分，硅锗合金部分，锗光电检测器和介电帽部分的叠层的悬垂结构。锗光电探测器由硅锗台面结构悬挂而不邻接硅波导。锗扩散到硅波导和锗检测器中的缺陷密度被最小化。

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