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1. 发明申请

US20080248626A1 SHALLOW TRENCH ISOLATION SELF-ALIGNED TO TEMPLATED RECRYSTALLIZATION BOUNDARY 审中-公开
标题翻译： SHOWOW TRENCH ISOLATION自对准至模拟重构边界
公开(公告)号：US20080248626A1
公开(公告)日：2008-10-09
申请号：US11697102
申请日：2007-04-05
申请人： Yaocheng Liu , Zhijiong Luo , Katherine L. Saenger , Chun-Yung Sung , Rajasekhar Venigalla , Haizhou Yin
发明人： Yaocheng Liu , Zhijiong Luo , Katherine L. Saenger , Chun-Yung Sung , Rajasekhar Venigalla , Haizhou Yin
IPC分类号： H01L21/762
CPC分类号： H01L21/26506 , H01L21/02667 , H01L21/187 , H01L21/76224
摘要： A hybrid orientation direct-semiconductor-bond (DSB) substrate with shallow trench isolation (STI) that is self-aligned to recrystallization boundaries is formed by patterning a hard mask layer for STI, a first amorphization implantation into openings in the hard mask layer, lithographic patterning of portions of a top semiconductor layer, a second amorphization implantation into exposed portions of the DSB substrate, recrystallization of the portions of the top semiconductor layer, and formation of STI utilizing the pattern in the hard mask layer. The edges of patterned photoresist for the second amorphization implantation are located within the openings in the patterned hard mask layer. Defective boundary regions formed underneath the openings in the hard mask layer are removed during the formation of STI to provide a leakage path free substrate. Due to elimination of a requirement for increased STI width, device density is increased compared to non-self-aligning process integration schemes.
摘要翻译：通过将STI的硬掩模层图案化，在硬掩模层的开口中进行第一非晶化注入，形成具有与重结晶边界自对准的浅沟槽隔离（STI）的混合取向直接半导体结合（DSB）顶部半导体层的部分的平版印刷图案化，第二非晶化注入到DSB衬底的暴露部分中，顶部半导体层的部分的再结晶，以及利用硬掩模层中的图案形成STI。用于第二非晶化注入的图案化光致抗蚀剂的边缘位于图案化的硬掩模层的开口内。在形成STI期间去除在硬掩模层中形成在开口下面的有缺陷的边界区域，以提供无泄漏路径的衬底。由于消除了对于增加的STI宽度的要求，与非自对准工艺集成方案相比，器件密度增加。

2. 发明授权

US07598147B2 Method of forming CMOS with Si:C source/drain by laser melting and recrystallization 有权
标题翻译：通过激光熔融和重结晶用Si：C源极/漏极形成CMOS的方法
公开(公告)号：US07598147B2
公开(公告)日：2009-10-06
申请号：US11860127
申请日：2007-09-24
申请人： Yaocheng Liu , Qiqing C. Ouyang , Kathryn T. Schonenberg , Chun-Yung Sung
发明人： Yaocheng Liu , Qiqing C. Ouyang , Kathryn T. Schonenberg , Chun-Yung Sung
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/268 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/665 , H01L29/66545 , H01L29/7848
摘要： A method of forming crystalline Si:C in source and drain regions is provided. After formation of shallow trench isolation and gate electrodes of field effect transistors, gate spacers are formed on gate electrodes. Preamorphization implantation is performed in the source and drain regions, followed by carbon implantation. The upper portion of the source and drain regions comprises an amorphous mixture of silicon, germanium, and/or carbon. An anti-reflective layer is deposited to enhance the absorption of a laser beam into the silicon substrate. The laser beam is scanned over the silicon substrate including the upper source and drain region with the amorphous mixture. The energy of the laser beam is controlled so that the temperature of the semiconductor substrate is above the melting temperature of the amorphous mixture but below the glass transition temperature of silicon oxide so that structural integrity of the semiconductor structure is preserved.
摘要翻译：提供了在源极和漏极区域中形成晶体Si：C的方法。在形成浅沟槽隔离和场效应晶体管的栅电极之后，在栅电极上形成栅极间隔物。在源极和漏极区域中进行前置放电，随后进行碳注入。源区和漏区的上部包括硅，锗和/或碳的无定形混合物。沉积抗反射层以增强激光束到硅衬底中的吸收。激光束在包括具有无定形混合物的上源极和漏极区域的硅衬底上扫描。控制激光束的能量使得半导体衬底的温度高于无定形混合物的熔融温度但低于氧化硅的玻璃化转变温度，从而保持半导体结构的结构完整性。

3. 发明申请

US20090081836A1 METHOD OF FORMING CMOS WITH SI:C SOURCE/DRAIN BY LASER MELTING AND RECRYSTALLIZATION 有权
标题翻译：通过激光熔化和重结晶形成CMOS与Si：C源/漏极的方法
公开(公告)号：US20090081836A1
公开(公告)日：2009-03-26
申请号：US11860127
申请日：2007-09-24
申请人： Yaocheng Liu , Qiqing C. Ouyang , Kathryn T. Schonenberg , Chun-Yung Sung
发明人： Yaocheng Liu , Qiqing C. Ouyang , Kathryn T. Schonenberg , Chun-Yung Sung
IPC分类号： H01L21/265 , H01L21/8238
CPC分类号： H01L21/26506 , H01L21/268 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/665 , H01L29/66545 , H01L29/7848
摘要： A method of forming crystalline Si:C in source and drain regions is provided. After formation of shallow trench isolation and gate electrodes of field effect transistors, gate spacers are formed on gate electrodes. Preamorphization implantation is performed in the source and drain regions, followed by carbon implantation. The upper portion of the source and drain regions comprises an amorphous mixture of silicon, germanium, and/or carbon. An anti-reflective layer is deposited to enhance the absorption of a laser beam into the silicon substrate. The laser beam is scanned over the silicon substrate including the upper source and drain region with the amorphous mixture. The energy of the laser beam is controlled so that the temperature of the semiconductor substrate is above the melting temperature of the amorphous mixture but below the glass transition temperature of silicon oxide so that structural integrity of the semiconductor structure is preserved.
摘要翻译：提供了在源极和漏极区域中形成晶体Si：C的方法。在形成浅沟槽隔离和场效应晶体管的栅电极之后，在栅电极上形成栅极间隔物。在源极和漏极区域中进行前置放电，随后进行碳注入。源区和漏区的上部包括硅，锗和/或碳的无定形混合物。沉积抗反射层以增强激光束到硅衬底中的吸收。激光束在包括具有无定形混合物的上源极和漏极区域的硅衬底上扫描。控制激光束的能量使得半导体衬底的温度高于无定形混合物的熔融温度但低于氧化硅的玻璃化转变温度，从而保持了半导体结构的结构完整性。

4. 发明授权

US07741658B2 Self-aligned super stressed PFET 有权
标题翻译：自对准超应力PFET
公开(公告)号：US07741658B2
公开(公告)日：2010-06-22
申请号：US11842437
申请日：2007-08-21
申请人： Yaocheng Liu , Zhijiong Luo , Huilong Zhu
发明人： Yaocheng Liu , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L31/0328
CPC分类号： H01L21/26506 , H01L21/268 , H01L29/1054 , H01L29/165 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： The embodiments of the invention comprise a self-aligned super stressed p-type field effect transistor (PFET). More specifically, a field effect transistor comprises a channel region comprising N-doped material and a gate above the channel region. The field effect transistor also includes a source region on a first side of the channel region and a drain region on a second side of the channel region opposite the first side. The source and drain regions each comprise silicon germanium, wherein the silicon germanium has structural indicia of epitaxial growth.
摘要翻译：本发明的实施例包括自对准超应力p型场效应晶体管（PFET）。更具体地，场效应晶体管包括包含N掺杂材料的沟道区和沟道区上方的栅。场效应晶体管还包括在沟道区的第一侧上的源极区域和与第一侧相对的沟道区域的第二侧上的漏极区域。源极和漏极区域各自包含硅锗，其中硅锗具有外延生长的结构标记。

5. 发明授权

US07473608B2 N-channel MOSFETs comprising dual stressors, and methods for forming the same 有权
标题翻译：包含双重应力的N沟道MOSFET及其形成方法
公开(公告)号：US07473608B2
公开(公告)日：2009-01-06
申请号：US11840795
申请日：2007-08-17
申请人： Jinghong H. Li , Yaocheng Liu , Zhijiong Luo , Anita Madan , Nivo Rovedo
发明人： Jinghong H. Li , Yaocheng Liu , Zhijiong Luo , Anita Madan , Nivo Rovedo
IPC分类号： H01L21/22
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/324 , H01L21/823807 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848 , Y10S257/90
摘要： The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.
摘要翻译：本发明涉及包括至少一个n沟道场效应晶体管（n-FET）的半导体器件。具体地说，n-FET包括第一和第二图案应力层，它们都包含碳取代和拉伸应力单晶半导体。第一图案应力层具有第一碳浓度并且位于第一深度处的n-FET的源极和漏极（S / D）延伸区域中。第二图案应力层具有第二较高的碳浓度，并且位于第二较深深度处的n-FET的S / D区中。这种具有不同碳浓度和不同深度的第一和第二图案应力层的n-FET提供了改善的应力分布，用于增强n-FET的沟道区域中的电子迁移率。

6. 发明申请

US20070281413A1 N-CHANNEL MOSFETS COMPRISING DUAL STRESSORS, AND METHODS FOR FORMING THE SAME 有权
标题翻译：包含双重压力机的N沟道MOSFET及其形成方法
公开(公告)号：US20070281413A1
公开(公告)日：2007-12-06
申请号：US11840795
申请日：2007-08-17
申请人： Jinghong Li , Yaocheng Liu , Zhijiong Luo , Anita Madan , Nivo Rovedo
发明人： Jinghong Li , Yaocheng Liu , Zhijiong Luo , Anita Madan , Nivo Rovedo
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/324 , H01L21/823807 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848 , Y10S257/90
摘要： The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.
摘要翻译：本发明涉及包括至少一个n沟道场效应晶体管（n-FET）的半导体器件。具体地说，n-FET包括第一和第二图案应力层，它们都包含碳取代和拉伸应力单晶半导体。第一图案应力层具有第一碳浓度并且位于第一深度处的n-FET的源极和漏极（S / D）延伸区域中。第二图案应力层具有第二较高的碳浓度，并且位于第二较深深度处的n-FET的S / D区中。这种具有不同碳浓度和不同深度的第一和第二图案应力层的n-FET提供了改善的应力分布，用于增强n-FET的沟道区域中的电子迁移率。

7. 发明申请

US20090050942A1 SELF-ALIGNED SUPER STRESSED PFET 有权
标题翻译：自对准超级应力PFET
公开(公告)号：US20090050942A1
公开(公告)日：2009-02-26
申请号：US11842437
申请日：2007-08-21
申请人： Yaocheng Liu , Zhijiong Luo , Huilong Zhu
发明人： Yaocheng Liu , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/268 , H01L29/1054 , H01L29/165 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： The embodiments of the invention comprise a self-aligned super stressed p-type field effect transistor (PFET). More specifically, a field effect transistor comprises a channel region comprising N-doped material and a gate above the channel region. The field effect transistor also includes a source region on a first side of the channel region and a drain region on a second side of the channel region opposite the first side. The source and drain regions each comprise silicon germanium, wherein the silicon germanium has structural indicia of epitaxial growth.
摘要翻译：本发明的实施例包括自对准超应力p型场效应晶体管（PFET）。更具体地，场效应晶体管包括包含N掺杂材料的沟道区和沟道区上方的栅。场效应晶体管还包括在沟道区的第一侧上的源极区域和与第一侧相对的沟道区域的第二侧上的漏极区域。源极和漏极区域各自包含硅锗，其中硅锗具有外延生长的结构标记。

8. 发明申请

US20080185636A1 SEMICONDUCTOR STRUCTURE INCLUDING DOPED SILICON CARBON LINER LAYER AND METHOD FOR FABRICATION THEREOF 有权
标题翻译：包括掺杂硅碳板层的半导体结构及其制造方法
公开(公告)号：US20080185636A1
公开(公告)日：2008-08-07
申请号：US11672109
申请日：2007-02-07
申请人： Zhijiong Luo , Yaocheng Liu
发明人： Zhijiong Luo , Yaocheng Liu
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66545 , H01L29/1083 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7834
摘要： A semiconductor structure and related method for fabrication thereof includes a liner layer interposed between: (1) a pedestal shaped channel region within a semiconductor substrate; and (2) a source region and a drain region within a semiconductor material layer located upon the liner layer and further laterally separated from the pedestal shaped channel region within the semiconductor substrate. The liner layer comprises an active doped silicon carbon material. The semiconductor material layer may comprises a semiconductor material other than a silicon carbon semiconductor material. The semiconductor material layer may alternatively comprise a silicon carbon semiconductor material having an opposite dopant polarity and lower carbon content in comparison with the liner layer. Due to presence of the silicon carbon material, the liner layer inhibits dopant diffusion therefrom into the pedestal shaped channel region. Electrical performance of a field effect device that uses the pedestal shaped channel region is thus enhanced.
摘要翻译：半导体结构及其相关制造方法包括：衬垫层，介于：（1）半导体衬底内的基座形沟道区; 以及（2）位于衬里层上的半导体材料层内的源极区域和漏极区域，并且与半导体衬底内的基座形状沟道区域进一步横向分离。衬里层包括有源掺杂硅碳材料。半导体材料层可以包括除了硅碳半导体材料之外的半导体材料。可选地，半导体材料层可以包含与衬里层相比具有相反掺杂剂极性和较低碳含量的硅碳半导体材料。由于存在硅碳材料，衬垫层阻止掺杂剂从其中扩散到基座形沟道区域中。因此，增强了使用基座形状的通道区域的场效应装置的电气性能。

9. 发明授权

US07279758B1 N-channel MOSFETs comprising dual stressors, and methods for forming the same 有权
标题翻译：包含双重应力的N沟道MOSFET及其形成方法
公开(公告)号：US07279758B1
公开(公告)日：2007-10-09
申请号：US11420047
申请日：2006-05-24
申请人： Jinghong H. Li , Yaocheng Liu , Zhijiong Luo , Anita Madan , Nivo Rovedo
发明人： Jinghong H. Li , Yaocheng Liu , Zhijiong Luo , Anita Madan , Nivo Rovedo
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/324 , H01L21/823807 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848 , Y10S257/90
摘要： The present invention relates to a semiconductor device including at least one n-channel field effect transistor (n-FET). Specifically, the n-FET includes first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.
摘要翻译：本发明涉及包括至少一个n沟道场效应晶体管（n-FET）的半导体器件。具体地说，n-FET包括均包含碳取代和拉伸应力单晶半导体的第一和第二图案应力层。第一图案应力层具有第一碳浓度并且位于第一深度处的n-FET的源极和漏极（S / D）延伸区域中。第二图案应力层具有第二较高的碳浓度，并且位于第二较深深度处的n-FET的S / D区中。这种具有不同碳浓度和不同深度的第一和第二图案应力层的n-FET提供了改善的应力分布，用于增强n-FET的沟道区域中的电子迁移率。

10. 发明授权

US07667263B2 Semiconductor structure including doped silicon carbon liner layer and method for fabrication thereof 有权
标题翻译：包括掺杂硅碳衬层的半导体结构及其制造方法
公开(公告)号：US07667263B2
公开(公告)日：2010-02-23
申请号：US11672109
申请日：2007-02-07
申请人： Zhijiong Luo , Yaocheng Liu
发明人： Zhijiong Luo , Yaocheng Liu
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L29/1083 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7834
摘要： A semiconductor structure and related method for fabrication thereof includes a liner layer interposed between: (1) a pedestal shaped channel region within a semiconductor substrate; and (2) a source region and a drain region within a semiconductor material layer located upon the liner layer and further laterally separated from the pedestal shaped channel region within the semiconductor substrate. The liner layer comprises an active doped silicon carbon material. The semiconductor material layer may comprises a semiconductor material other than a silicon carbon semiconductor material. The semiconductor material layer may alternatively comprise a silicon carbon semiconductor material having an opposite dopant polarity and lower carbon content in comparison with the liner layer. Due to presence of the silicon carbon material, the liner layer inhibits dopant diffusion therefrom into the pedestal shaped channel region. Electrical performance of a field effect device that uses the pedestal shaped channel region is thus enhanced.
摘要翻译：半导体结构及其相关制造方法包括：衬垫层，介于：（1）半导体衬底内的基座形沟道区; 以及（2）位于衬里层上的半导体材料层内的源极区域和漏极区域，并且与半导体衬底内的基座形状沟道区域进一步横向分离。衬里层包括有源掺杂硅碳材料。半导体材料层可以包括除了硅碳半导体材料之外的半导体材料。可选地，半导体材料层可以包含与衬里层相比具有相反掺杂剂极性和较低碳含量的硅碳半导体材料。由于存在硅碳材料，衬垫层阻止掺杂剂从其中扩散到基座形沟道区域中。因此，增强了使用基座形状的通道区域的场效应装置的电气性能。

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