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1. 发明授权

US06975032B2 Copper recess process with application to selective capping and electroless plating 有权
公开(公告)号：US06975032B2
公开(公告)日：2005-12-13
申请号：US10319967
申请日：2002-12-16
申请人： Shyng-Tsong Chen , Timothy J. Dalton , Kenneth M. Davis , Chao-Kun Hu , Fen F. Jamin , Steffen K. Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael F. Lofaro , Sandra G. Malhotra , Chandrasekhar Narayan , David L. Rath , Judith M. Rubino , Katherine L. Saenger , Andrew H. Simon , Sean P. E. Smith , Wei-tsu Tseng
发明人： Shyng-Tsong Chen , Timothy J. Dalton , Kenneth M. Davis , Chao-Kun Hu , Fen F. Jamin , Steffen K. Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael F. Lofaro , Sandra G. Malhotra , Chandrasekhar Narayan , David L. Rath , Judith M. Rubino , Katherine L. Saenger , Andrew H. Simon , Sean P. E. Smith , Wei-tsu Tseng
IPC分类号： H01L21/768 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/76847 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

2. 发明授权

US07064064B2 Copper recess process with application to selective capping and electroless plating 有权
标题翻译：铜凹槽工艺，适用于选择性封盖和无电镀
公开(公告)号：US07064064B2
公开(公告)日：2006-06-20
申请号：US11058783
申请日：2005-02-16
申请人： Shyng-Tsong Chen , Timothy J. Dalton , Kenneth M. Davis , Chao-Kun Hu , Fen F. Jamin , Steffen K. Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael F. Lofaro , Sandra G. Malhotra , Chandrasekhar Narayan , David L. Rath , Judith M. Rubino , Katherine L. Saenger , Andrew H. Simon , Sean P. E. Smith , Wei-tsu Tseng
发明人： Shyng-Tsong Chen , Timothy J. Dalton , Kenneth M. Davis , Chao-Kun Hu , Fen F. Jamin , Steffen K. Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael F. Lofaro , Sandra G. Malhotra , Chandrasekhar Narayan , David L. Rath , Judith M. Rubino , Katherine L. Saenger , Andrew H. Simon , Sean P. E. Smith , Wei-tsu Tseng
IPC分类号： H01L21/44
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/76847 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.
摘要翻译：公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。

3. 发明授权

US07494915B2 Back end interconnect with a shaped interface 失效
标题翻译：后端互连与成形接口
公开(公告)号：US07494915B2
公开(公告)日：2009-02-24
申请号：US11463447
申请日：2006-08-09
申请人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Erdem Kaltalioglu , Kaushik A. Kumar , Douglas C. La Tulipe, Jr. , Jochen Schacht , Andrew H. Simon , Terry A. Spooner , Yun-Yu Wang , Clement H. Wann , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Erdem Kaltalioglu , Kaushik A. Kumar , Douglas C. La Tulipe, Jr. , Jochen Schacht , Andrew H. Simon , Terry A. Spooner , Yun-Yu Wang , Clement H. Wann , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76807 , H01L21/76814 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.
摘要翻译：在集成电路的线的后端中的互连结构通过在锥形孔中去除下互连的顶表面中的材料而形成连续层之间的接触，该去除过程延伸穿过上孔的衬垫，以及沉积向下延伸到锥形孔中的第二衬垫，从而增加接触件的机械强度，从而提高集成电路的整体可靠性。

4. 发明授权

US07122462B2 Back end interconnect with a shaped interface 有权
公开(公告)号：US07122462B2
公开(公告)日：2006-10-17
申请号：US10707122
申请日：2003-11-21
申请人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Erdem Kaltalioglu , Kaushik A. Kumar , Douglas C. La Tulipe, Jr. , Jochen Schacht , Andrew H. Simon , Terry A. Spooner , Yun-Yu Wang , Clement H. Wann , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Erdem Kaltalioglu , Kaushik A. Kumar , Douglas C. La Tulipe, Jr. , Jochen Schacht , Andrew H. Simon , Terry A. Spooner , Yun-Yu Wang , Clement H. Wann , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76807 , H01L21/76814 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

5. 发明授权

US07001835B2 Crystallographic modification of hard mask properties 失效
标题翻译：硬掩模性能的晶体学修饰
公开(公告)号：US07001835B2
公开(公告)日：2006-02-21
申请号：US10707119
申请日：2003-11-21
申请人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Kaushik A. Kumar , Stephen M. Rossnagel , Andrew H. Simon , Douglas C. La Tulipe, Jr.
发明人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Kaushik A. Kumar , Stephen M. Rossnagel , Andrew H. Simon , Douglas C. La Tulipe, Jr.
IPC分类号： H01L21/4763
CPC分类号： H01L23/544 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L21/0332 , H01L21/0337 , H01L21/2855 , H01L21/76841 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A hardmask layer in the back end of an integrated circuit is formed from TaN having a composition of less than 50% Ta and a resistivity greater than 400 μOhm-cm, so that it is substantially transparent in the visible and permits visual alignment of upper and lower alignment marks through the hardmask and intervening layer(s) of ILD. A preferred method of formation of the hardmask is by sputter deposition of Ta in an ambient containing N2 and a flow rate such that (N2 flow)/(N2+carrier flow)>0.5.
摘要翻译：集成电路后端的硬掩模层由具有小于50％Ta且电阻率大于400μΩ-cm的组成的TaN形成，使得其在可见光中基本上是透明的并且允许上和通过硬掩模和ILD的中间层降低对准标记。形成硬掩模的优选方法是通过在含有N 2 O 2的环境中溅射沉积Ta并使流速使得（N 2 N 2 O 2）/（N _{2 +载体流）> 0.5。}

6. 发明授权

US07052621B2 Bilayered metal hardmasks for use in Dual Damascene etch schemes 有权
标题翻译：用于双镶嵌蚀刻方案的双层金属硬掩模
公开(公告)号：US07052621B2
公开(公告)日：2006-05-30
申请号：US10461090
申请日：2003-06-13
申请人： Kaushik Kumar , Lawrence Clevenger , Timothy Dalton , Douglas C. La Tulipe , Andy Cowley , Erdem Kaltalioglu , Jochen Schacht , Andrew H. Simon , Mark Hoinkis , Steffen K. Kaldor , Chih-Chao Yang
发明人： Kaushik Kumar , Lawrence Clevenger , Timothy Dalton , Douglas C. La Tulipe , Andy Cowley , Erdem Kaltalioglu , Jochen Schacht , Andrew H. Simon , Mark Hoinkis , Steffen K. Kaldor , Chih-Chao Yang
IPC分类号： C23F1/00
CPC分类号： H01L21/76832 , H01L21/0332 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L2221/1036 , Y10T428/12576 , Y10T428/12806 , Y10T428/265 , Y10T428/31678
摘要： A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).
摘要翻译：用于制造半导体器件的双镶嵌工艺的金属硬掩模。金属硬掩模具有有利的半透明特性，以有助于在制造半导体器件时水平之间的对准，并避免形成金属氧化物残留物沉积物。金属硬掩模包括TiN（氮化钛）的第一或第一层和TaN（氮化钽）的第二或覆盖层。

7. 发明授权

US07241681B2 Bilayered metal hardmasks for use in dual damascene etch schemes 有权
标题翻译：用于双镶嵌蚀刻方案的双层金属硬掩模
公开(公告)号：US07241681B2
公开(公告)日：2007-07-10
申请号：US11330834
申请日：2006-01-12
申请人： Kaushik Kumar , Lawrence Clevenger , Timothy Dalton , Douglas C. La Tulipe , Andy Cowley , Erdem Kaltalioglu , Jochen Schacht , Andrew H. Simon , Mark Hoinkis , Steffen K. Kaldor , Chih-Chao Yang
发明人： Kaushik Kumar , Lawrence Clevenger , Timothy Dalton , Douglas C. La Tulipe , Andy Cowley , Erdem Kaltalioglu , Jochen Schacht , Andrew H. Simon , Mark Hoinkis , Steffen K. Kaldor , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76832 , H01L21/0332 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L2221/1036 , Y10T428/12576 , Y10T428/12806 , Y10T428/265 , Y10T428/31678
摘要： A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).
摘要翻译：用于制造半导体器件的双镶嵌工艺的金属硬掩模。金属硬掩模具有有利的半透明特性，以有助于在制造半导体器件时水平之间的对准，并避免形成金属氧化物残留物沉积物。金属硬掩模包括TiN（氮化钛）的第一或第一层和TaN（氮化钽）的第二或覆盖层。

8. 发明授权

US07241696B2 Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer 失效
标题翻译：在具有覆盖层的半导体互连结构上沉积金属层的方法
公开(公告)号：US07241696B2
公开(公告)日：2007-07-10
申请号：US10318606
申请日：2002-12-11
申请人： Larry Clevenger , Timothy Joseph Dalton , Mark Hoinkis , Steffen K. Kaldor , Kaushik Kumar , Douglas C. La Tulipe, Jr. , Soon-Cheon Seo , Andrew Herbert Simon , Yun-Yu Wang , Chih-Chao Yang , Haining Yang
发明人： Larry Clevenger , Timothy Joseph Dalton , Mark Hoinkis , Steffen K. Kaldor , Kaushik Kumar , Douglas C. La Tulipe, Jr. , Soon-Cheon Seo , Andrew Herbert Simon , Yun-Yu Wang , Chih-Chao Yang , Haining Yang
IPC分类号： H01L21/00
CPC分类号： H01L21/76843 , H01L21/76805 , H01L21/76807 , H01L21/76834 , H01L21/76835 , H01L21/76844 , H01L21/76847 , H01L21/76865
摘要： Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.
摘要翻译：公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。在该方法中，金属导体被覆盖层和电介质层覆盖。对电介质层进行图案化以使覆盖层露出。然后溅射蚀刻覆盖层以去除覆盖层并暴露金属导体。在溅射蚀刻的过程中，覆盖层被再沉积到图案的侧壁上。最后，至少一层沉积到图案中并覆盖再沉积的覆盖层。

9. 发明授权

US07214548B2 Apparatus and method for flattening a warped substrate 失效
标题翻译：使翘曲基材变平的装置和方法
公开(公告)号：US07214548B2
公开(公告)日：2007-05-08
申请号：US10929179
申请日：2004-08-30
申请人： Mohammed F. Fayaz , Steffen K. Kaldor , Conal E. Murray , Ismail C. Noyan , Anne L. Petrosky
发明人： Mohammed F. Fayaz , Steffen K. Kaldor , Conal E. Murray , Ismail C. Noyan , Anne L. Petrosky
IPC分类号： H01L21/00
CPC分类号： H01L21/67288 , H01L21/6838
摘要： A method, apparatus, and computer program product for flattening a warped substrate. The substrate is placed on a planar surface of a clamping apparatus in direct mechanical contact with the planar surface. The substrate comprises surface regions S1, S2, . . . , SN having an average warpage of W1, W2, . . . , WN, respectively, wherein W1≦W2≦ . . . ≦WN and W1≦WN. Zones Z1, Z2, . . . , ZN of the planar surface respectively comprise vacuum port groups G1, G2, . . . , GN. Each group comprises at least one vacuum port. N is at least 2. A vacuum pressure PV1, PV2, . . . , PVN is generated at each vacuum port within group G1, G2, . . . , GN, at a time of T1, T2, . . . , TN to clamp surface region S1, S2, . . . , SN to zone Z1, Z2, . . . , ZN, respectively. The vacuum pressure PV1, PV2, . . . , PVN is maintained at the vacuum ports of group G1, G2, . . . , GN, respectively, until time TN+1. T1
摘要翻译：一种用于使翘曲的基底平坦化的方法，装置和计算机程序产品。基板被放置在与平面表面直接机械接触的夹紧装置的平面表面上。衬底包括表面区域S 1，S 2，...。。。具有W 1，W 2 2的平均翘曲的S N N N。。。，其中W 1分别为W 1，其中W 1为= W 2 N。。。＆lt; N＆gt;和＆lt; 1＆lt; 1＆gt;＆lt; N＆lt; N＆gt; Z区Z 1，Z 2 2，。。。平面的Z N N分别包括真空端口组G 1，G 2，...。。。，G N N。每个组包括至少一个真空端口。 N至少为2.真空压力P V1，P2 S2。。。在组G 1，G 2 2中的每个真空端口处产生P 。。。在T 1时，T 2时，G N，N N 3。。。，T N N夹紧表面区域S 1，S 2，N 2。。。，Z N 1，Z 2，...，Z N 2。。。，Z N N 3。真空压力P ，P ，。。，P N 2保持在组G 1，G 2 2的真空端口。。。，分别为N N + 1，直到时间T N + 1。 T 1 。。。 N + 1 N + 1。

10. 发明授权

US07098537B2 Interconnect structure diffusion barrier with high nitrogen content 有权
标题翻译：具有高氮含量的互连结构扩散阻挡层
公开(公告)号：US07098537B2
公开(公告)日：2006-08-29
申请号：US10707117
申请日：2003-11-21
申请人： Cyril Cabral, Jr. , Steffen K. Kaldor , Hyungjun Kim , Stephen M. Rossnagel
发明人： Cyril Cabral, Jr. , Steffen K. Kaldor , Hyungjun Kim , Stephen M. Rossnagel
IPC分类号： H01L23/52 , H01L23/48
CPC分类号： H01L21/76843 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In an interconnect structure of an integrated circuit, a diffusion barrier film in a damascene structure is formed of a film having the composition TaNx, where x is greater than 1.2 and with a thickness of 0.5 to 5 nm.
摘要翻译：在集成电路的互连结构中，镶嵌结构中的扩散阻挡膜由具有组成TaN x x的膜形成，其中x大于1.2，厚度为0.5至5nm 。

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