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71. 发明授权

US07226222B2 Laser module with sealed packages having reduced total volume 有权
标题翻译：具有密封包装的激光模块，总体积减小
公开(公告)号：US07226222B2
公开(公告)日：2007-06-05
申请号：US11197592
申请日：2005-08-05
申请人： Kazuhiko Nagano , Hideo Miura , Shinichiro Sonoda
发明人： Kazuhiko Nagano , Hideo Miura , Shinichiro Sonoda
IPC分类号： G02B6/36
CPC分类号： G02B6/4248 , G02B6/3897 , G02B6/4249 , G02B6/4292
摘要： In a laser module in which laser beams emitted from semiconductor laser elements are collimated by collimator lenses, and condensed by an optical condensing system so that the laser beams converge at a light-entrance end face of an optical fiber. The semiconductor laser elements and the collimator lenses are contained in a hermetically sealed, first package which includes a front wall having a window arranged for passage of the laser beams, and a portion of the optical condensing system and the light-entrance end face are contained in a hermetically sealed, second package which is fixed to the front wall. The cross section of the second package perpendicular to the optical axis of the optical fiber at the light-entrance end face is smaller than the cross section of the first package parallel to the cross section of the second package.
摘要翻译：在从半导体激光元件射出的激光束通过准直透镜准直的激光模块中，通过光聚光系统进行聚光，使得激光束会聚在光纤的光入射端面。半导体激光元件和准直透镜被包含在气密密封的第一封装中，该封装包括具有布置成用于激光束通过的窗口的前壁，并且包含光聚光系统和光入射端面的一部分在密封的第二包装中，其被固定到前壁。在光入射端面处垂直于光纤的光轴的第二封装的横截面小于与第二封装的横截面平行的第一封装的横截面。

72. 发明授权

US06907059B1 Optical component fixing method and optical component support 失效
标题翻译：光学部件固定方法和光学部件支撑
公开(公告)号：US06907059B1
公开(公告)日：2005-06-14
申请号：US09534034
申请日：2000-03-24
申请人： Hideo Miura , Kazumi Kubo
发明人： Hideo Miura , Kazumi Kubo
IPC分类号： G02B7/00 , H01S3/02 , H01S3/08 , B32B17/00 , B32B31/00 , C03C27/00
CPC分类号： H01S3/025 , H01S3/0401 , H01S3/0405 , H01S3/042 , H01S3/09415 , Y10T156/1064
摘要： A method of fixing an optical component includes the steps of scoring a surface of a support, bringing an optical component into close contact with the scored surface of the support, and flowing a fluid adhesive along kerfs produced by the scoring. An optical component support has a surface provided with scoring kerts for fixing the optical component. The method and support enable fixing of an optical component by a thin, uniform adhesive layer, without fine polishing of the optical component and the surface of the support.
摘要翻译：固定光学部件的方法包括以下步骤：对支撑体的表面进行刻痕，使光学部件与支撑体的刻痕表面紧密接触，并且使流体粘合剂沿着由刻痕产生的切口流动。光学部件支撑件具有设置有用于固定光学部件的刻痕警报器的表面。该方法和支持使得能够通过薄的均匀的粘合剂层固定光学部件，而不会精细地抛光光学部件和支撑体的表面。

73. 发明申请

US20050079667A1 Semiconductor device and production method therefor 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050079667A1
公开(公告)日：2005-04-14
申请号：US10503350
申请日：2003-02-05
申请人： Tomio Iwasaki , Norio Ishitsuka , Hideo Miura
发明人： Tomio Iwasaki , Norio Ishitsuka , Hideo Miura
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8244 , H01L21/8247 , H01L27/11 , H01L27/115 , H01L29/49 , H01L29/78 , H01L29/788 , H01L29/792 , H01L21/425 , H01L21/8234 , H01L21/8238 , H01L29/76 , H01L29/94
CPC分类号： H01L29/6659 , H01L21/26513 , H01L29/4925 , H01L29/4983 , H01L29/7833
摘要： A semiconductor device having a high degree of reliability is provided. A second object of the invention is to provide a semiconductor device of high yield. The semiconductor includes a silicon substrate, a gate dielectric film formed on one main surface of the silicon substrate, a gate electrode formed by being stacked on the gate dielectric film and a diffusion layer containing arsenic and phosphorus. Both of the concentration of the highest concentration portion of arsenic and the concentration of the highest concentration portion of phosphorus are each at 1026 atoms/m3 or more and 1027 atoms/m3 or less, and the depth of the highest concentration portion of phosphorus from the surface of the silicon substrate is less than the depth of the highest concentration portion of arsenic.
摘要翻译：提供了具有高可靠性的半导体器件。本发明的第二个目的是提供一种高产率的半导体器件。半导体包括硅衬底，形成在硅衬底的一个主表面上的栅极电介质膜，通过层叠在栅极电介质膜上形成的栅电极和含有砷和磷的扩散层。砷的最高浓度部分的浓度和磷的最高浓度部分的浓度分别为10 26个/ m 3以上且10 27个/ m 3以下，并且来自硅衬底的表面的磷的最高浓度部分的深度小于砷的最高浓度部分的深度。

74. 发明授权

US06856021B1 Semiconductor device having aluminum alloy conductors 失效
标题翻译：具有铝合金导体的半导体器件
公开(公告)号：US06856021B1
公开(公告)日：2005-02-15
申请号：US09648455
申请日：2000-08-28
申请人： Tomio Iwasaki , Hideo Miura , Takashi Nakajima , Hiroyuki Ohta , Shinji Nishihara , Masashi Sahara
发明人： Tomio Iwasaki , Hideo Miura , Takashi Nakajima , Hiroyuki Ohta , Shinji Nishihara , Masashi Sahara
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/532
CPC分类号： H01L21/76844 , H01L21/32051 , H01L21/76843 , H01L21/7685 , H01L23/53219 , H01L23/53223 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided which includes a semiconductor substrate, metal conductors formed on a side of a main face of the substrate, which metal conductors contain aluminum as a main constituent thereof, and copper as an additive element, the metal conductors being made to contain such an element as to suppress the precipitation of copper or being made to have such a film adjacent to the metal conductor as to suppress the precipitation of copper or being made to have such a film adjacent to the metal conductor as to suppress the precipitation of copper.
摘要翻译：提供了一种半导体器件，其包括半导体衬底，形成在衬底的主面一侧的金属导体，该金属导体以铝为主要成分，铜作为添加元素，金属导体被制成含有抑制铜的析出或使金属导体附近具有这样的膜的元素，以抑制铜的沉淀，或者使该膜与金属导体相邻，以抑制铜的析出。

75. 发明申请

US20050032252A1 Testing apparatus for carrying out inspection of a semiconductor device 有权
标题翻译：用于对半导体器件进行检查的测试装置
公开(公告)号：US20050032252A1
公开(公告)日：2005-02-10
申请号：US10934046
申请日：2004-09-03
申请人： Ryuji Kohno , Hideo Miura , Masatoshi Kanamaru , Hiroya Shimizu , Hideyuki Aoki
发明人： Ryuji Kohno , Hideo Miura , Masatoshi Kanamaru , Hiroya Shimizu , Hideyuki Aoki
IPC分类号： G01R1/06 , G01R1/073 , G01R31/28 , H01L21/66 , G01R31/02 , G01R31/26
CPC分类号： G01R1/07314
摘要： A method of manufacturing a semiconductor device has forming process for forming a semiconductor device on a major surface of a wafer, and testing process for testing defect of the semiconductor device formed on the wafer. The testing process includes a step bringing a testing apparatus into contact with test electrodes of the semiconductor device. The testing apparatus has a contactor including a plurality of probes that come into contact with the test electrodes of the semiconductor device to be tested, and secondary electrodes electrically connected to the probes and disposed on a surface opposite to the probes; a substrate on which electrodes electrically communicated to the contactor by a conducting device. The conducting device is so formed that stress applied to the conducting device in the state where the probes are in contact with the test electrodes is larger than stress applied to the conducting device in the state where the probes are not in contact with the test electrodes.
摘要翻译：制造半导体器件的方法具有在晶片的主表面上形成半导体器件的形成工艺和用于测试形成在晶片上的半导体器件的缺陷的测试过程。测试过程包括使测试设备与半导体器件的测试电极接触的步骤。测试装置具有接触器，该接触器包括与待测半导体器件的测试电极接触的多个探针，以及与探针电连接并设置在与探针相对的表面上的二次电极; 电极通过导电装置与接触器电连通的基板。导电装置形成为在探针与测试电极接触的状态下施加到导电装置的应力大于在探针不与测试电极接触的状态下施加到导电装置的应力。

76. 发明授权

US06803294B2 Semiconductor wafer and manufacturing method of semiconductor device 有权
标题翻译：半导体晶圆及半导体器件的制造方法
公开(公告)号：US06803294B2
公开(公告)日：2004-10-12
申请号：US10413562
申请日：2003-04-15
申请人： Yasuhiko Kouno , Hideo Miura , Nobuyoshi Matsuura , Masaharu Kubo
发明人： Yasuhiko Kouno , Hideo Miura , Nobuyoshi Matsuura , Masaharu Kubo
IPC分类号： H01L2146
CPC分类号： H01L29/66333 , H01L21/304 , H01L21/78 , H01L24/05 , H01L24/45 , H01L29/7395 , H01L2224/04042 , H01L2224/32145 , H01L2224/32245 , H01L2224/45144 , H01L2224/48145 , H01L2224/48247 , H01L2224/48472 , H01L2224/4911 , H01L2224/73265 , H01L2924/10158 , H01L2924/10253 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00014 , H01L2924/00012
摘要： Gate oxide films, gate electrodes, base regions and emitter regions, which constitute IGBTs, are formed on a semiconductor wafer. A silicon oxide film is formed on the gate electrodes. Further, an emitter electrode is formed thereabove, and a passivation film is formed over the emitter electrode. Thereafter, an internal area of a back surface of the semiconductor wafer is polished to form a protrusion at its outer peripheral portion. Afterwards, an impurity is injected from the back surface of the semiconductor wafer to form a collector region. After a collector electrode is further formed, the semiconductor wafer is mounted on a stage smaller than the internal area and subjected to dicing along scribe areas. Thus, the strength of the semiconductor wafer is held by the protrusion, and cracking or the like of the semiconductor wafer can be reduced owing to the execution of the dicing in the above-described manner.
摘要翻译：构成IGBT的栅极氧化膜，栅极电极，基极区域和发射极区域形成在半导体晶片上。在栅电极上形成氧化硅膜。此外，在上方形成发射电极，在发射电极上形成钝化膜。此后，对半导体晶片的背面的内部区域进行研磨，在其外周部形成突起。之后，从半导体晶片的背面注入杂质，形成集电极区域。在进一步形成集电极之后，将半导体晶片安装在小于内部区域的台上，并沿划线区进行切割。因此，半导体晶片的强度由突起保持，并且由于以上述方式执行切割，可以减小半导体晶片的破裂等。

77. 发明授权

US06784533B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06784533B2
公开(公告)日：2004-08-31
申请号：US10212104
申请日：2002-08-06
申请人： Hiroya Shimizu , Asao Nishimura , Tosiho Miyamoto , Hideki Tanaka , Hideo Miura
发明人： Hiroya Shimizu , Asao Nishimura , Tosiho Miyamoto , Hideki Tanaka , Hideo Miura
IPC分类号： H01L2352
CPC分类号： H01L24/10 , H01L23/50 , H01L23/5286 , H01L23/552 , H01L23/645 , H01L23/66 , H01L24/13 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05569 , H01L2224/05571 , H01L2224/05572 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device is provided which is highly reliable and operable at fast speed and low noises. In this semiconductor device, there are provided a power wiring section 1003a, a ground wiring section 1003b and a signal wiring section 1003c are formed on one level. The power wiring section or the ground wiring section is formed adjacently on both sides of at least one part of the signal wiring section.
摘要翻译：提供了一种高度可靠并且以高速度和低噪声操作的半导体器件。在该半导体装置中，在一个层上形成有电力配线部1003a，接地配线部1003b以及信号配线部1003c。功率配线部或接地配线部形成在信号配线部的至少一部分的两侧上。

78. 发明授权

US06692686B1 Blow molding method and apparatus 有权
标题翻译：吹塑法和设备
公开(公告)号：US06692686B1
公开(公告)日：2004-02-17
申请号：US09557572
申请日：2000-04-25
申请人： Toshiaki Gonda , Hideo Miura , Hiroshi Noma , Takashi Miyazaki
发明人： Toshiaki Gonda , Hideo Miura , Hiroshi Noma , Takashi Miyazaki
IPC分类号： B29C4904
CPC分类号： B29C49/32 , B29C49/04 , B29C49/16 , B29C49/2408 , B29C49/421 , B29C49/4236 , B29C49/66 , B29C49/72 , B29C2049/2412 , B29C2049/2449 , B29C2049/2456 , B29C2049/325 , B29C2049/5875 , B29C2049/6027 , B29C2049/6036 , B29C2049/6615
摘要： A blow molding method includes steps of moving a split mold to a parison receiving position where a parison is supplied and receiving a parison, closing the split mold, performing blow molding at a blow molding position, and opening the split mold at a product discharge position and thereby discharging a product. The method further includes steps of: sequentially reciprocating each split mold in trains of split molds provided opposed to each other across the parison receiving position to and from a position opposed to the parison receiving position; and sequentially reciprocating the split mold disposed at the position where the split mold is opposed to the parsion receiving position to and from the parison receiving position for performing blow molding. There is also provided a blow molding apparatus for carrying out this molding method.
摘要翻译：吹塑成型方法包括以下步骤：将分型模移动到型坯接收位置，在型坯接收位置供给型坯，接收型坯，闭合分模，在吹塑成型位置进行吹塑成型，并在产品排出位置打开分模从而排出产品。该方法还包括以下步骤：顺序地将分开的模具中的每个分割模具往相互对置的分型模具的列中相对地穿过所述型坯接收位置并从与所述型坯接收位置相对的位置移动; 并且将配置在与模型接收位置相对的位置处的分割模具依次往往与用于进行吹塑成形的型坯接收位置往复运动。还提供了一种用于实施该成型方法的吹塑装置。

79. 发明授权

US06566149B1 Method for manufacturing substrate for inspecting semiconductor device 失效
标题翻译：用于检查半导体器件的衬底的制造方法
公开(公告)号：US06566149B1
公开(公告)日：2003-05-20
申请号：US09787250
申请日：2001-03-16
申请人： Masatoshi Kanamaru , Atsushi Hosogane , Yoshihige Endou , Ryuji Kouno , Hideo Miura , Shinji Tanaka , Hiroyuki Ohta , Akihiko Ariga , Naoto Ban , Hideyuki Aoki
发明人： Masatoshi Kanamaru , Atsushi Hosogane , Yoshihige Endou , Ryuji Kouno , Hideo Miura , Shinji Tanaka , Hiroyuki Ohta , Akihiko Ariga , Naoto Ban , Hideyuki Aoki
IPC分类号： G01R3126
CPC分类号： G01R3/00
摘要： For an inspection tray, a silicon substrate including a beam or a diaphragm, a probe and wiring is used. To highly accurately position a chip to be inspected, a second substrate for alignment is disposed on the substrate. To position the probe having wiring disposed on the first substrate and the electrode pad of the chip to be inspected, a projection or a groove is formed in each of both substrates. Preferably, the projection or groove should be formed by silicon anisotorpic etching to have a (111) crystal surface. As another machining method, dry etching can be used for machining the positioning projection or groove. By using an inductively coupled plasma-reactive ion etching (ICP-RIE) device for the dry etching, a vertical column or groove can be easily machined.
摘要翻译：对于检查托盘，使用包括梁或隔膜，探针和布线的硅基板。为了高精度地定位待检查的芯片，在基板上设置用于对准的第二基板。为了定位具有设置在第一基板上的布线的探针和要检查的芯片的电极焊盘，在两个基板中的每一个中形成突起或凹槽。优选地，突起或凹槽应由硅各向异性蚀刻形成以具有（111）晶体表面。作为另一种加工方法，可以使用干蚀刻来加工定位突起或凹槽。通过使用用于干蚀刻的电感耦合等离子体反应离子蚀刻（ICP-RIE）装置，可以容易地加工垂直的柱或槽。

80. 发明授权

US06544884B2 Semiconductor device and method of fabricating same 失效
公开(公告)号：US06544884B2
公开(公告)日：2003-04-08
申请号：US10022525
申请日：2001-12-20
申请人： Hiroyuki Ohta , Hideo Miura , Kazushige Sato , Takeshi Kimura , Hiyoo Masuda
发明人： Hiroyuki Ohta , Hideo Miura , Kazushige Sato , Takeshi Kimura , Hiyoo Masuda
IPC分类号： H01L214763
CPC分类号： H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device capable of operating at a high speed or of having many functions. In this device, delamination of buried electrodes is prevented and thus high reliability is offered. The depth A of contact holes, the minimum linewidth R of a lower metallization layer, and the thickness B of the lower metallization layer satisfy relations given by (0.605/R)0.5

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