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1. 发明授权

US07371687B2 Electronic circuit device 失效
标题翻译：电子电路装置
公开(公告)号：US07371687B2
公开(公告)日：2008-05-13
申请号：US11475961
申请日：2006-06-28
申请人： Ryo Fujita , Osamu Kubo , Kouki Noguchi , Masaharu Kubo , Michihiro Mishima , Yasuhiko Takahashi
发明人： Ryo Fujita , Osamu Kubo , Kouki Noguchi , Masaharu Kubo , Michihiro Mishima , Yasuhiko Takahashi
IPC分类号： H01L23/52
CPC分类号： G06F11/261 , G06F11/267 , G06F15/7867 , H01L25/18 , H01L2224/16225 , H01L2924/00014 , H01L2924/09701 , H01L2924/13091 , H01L2924/15192 , H01L2924/15311 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory (16) which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated. Consequently, the device facilitates the debugging at early stages of system development, configures a prototype system, and contributes to the time reduction throughout the system development, prototype fabrication and large-scale production.
摘要翻译：电子电路装置具有高密度安装板（2），微型计算机（3）和随机存取存储器（7）设置在其上，通过用于高速数据的专用存储器总线（12）彼此连接传输，由FPGA表示的可变逻辑电路的可编程器件（8）和可存储微型计算机的操作程序的电可重写非易失性存储器（16）。高密度安装板在底面上具有外部安装销，使其可以以与系统片上多芯片模块相同的方式安装在母板上。通过在可编程器件上设置预期的逻辑功能，可以模拟由电子电路器件实现的基于硬件的功能。通过将操作程序写入非易失性存储器，可以模拟要实现的基于软件的功能。因此，该设备便于系统开发初期的调试，配置原型系统，有助于整个系统开发，原型制作和大规模生产的时间缩短。

2. 发明申请

US20060244122A1 Electronic circuit device 失效
标题翻译：电子电路装置
公开(公告)号：US20060244122A1
公开(公告)日：2006-11-02
申请号：US11475936
申请日：2006-06-28
申请人： Ryo Fujita , Osamu Kubo , Kouki Noguchi , Masaharu Kubo , Michihiro Mishima , Yasuhiko Takahashi
发明人： Ryo Fujita , Osamu Kubo , Kouki Noguchi , Masaharu Kubo , Michihiro Mishima , Yasuhiko Takahashi
IPC分类号： H01L23/52
CPC分类号： G06F11/261 , G06F11/267 , G06F15/7867 , H01L25/18 , H01L2224/16225 , H01L2924/00014 , H01L2924/09701 , H01L2924/13091 , H01L2924/15192 , H01L2924/15311 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory (16) which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated. Consequently, the device facilitates the debugging at early stages of system development, configures a prototype system, and contributes to the time reduction throughout the system development, prototype fabrication and large-scale production.
摘要翻译：电子电路装置具有高密度安装板（2），微型计算机（3）和随机存取存储器（7）设置在其上，通过用于高速数据的专用存储器总线（12）彼此连接传输，由FPGA表示的可变逻辑电路的可编程器件（8）和可存储微型计算机的操作程序的电可重写非易失性存储器（16）。高密度安装板在底面上具有外部安装销，使其可以以与系统片上多芯片模块相同的方式安装在母板上。通过在可编程器件上设置预期的逻辑功能，可以模拟由电子电路器件实现的基于硬件的功能。通过将操作程序写入非易失性存储器，可以模拟要实现的基于软件的功能。因此，该设备便于系统开发初期的调试，配置原型系统，有助于整个系统开发，原型制作和大规模生产的时间缩短。

3. 发明授权

US06803294B2 Semiconductor wafer and manufacturing method of semiconductor device 有权
标题翻译：半导体晶圆及半导体器件的制造方法
公开(公告)号：US06803294B2
公开(公告)日：2004-10-12
申请号：US10413562
申请日：2003-04-15
申请人： Yasuhiko Kouno , Hideo Miura , Nobuyoshi Matsuura , Masaharu Kubo
发明人： Yasuhiko Kouno , Hideo Miura , Nobuyoshi Matsuura , Masaharu Kubo
IPC分类号： H01L2146
CPC分类号： H01L29/66333 , H01L21/304 , H01L21/78 , H01L24/05 , H01L24/45 , H01L29/7395 , H01L2224/04042 , H01L2224/32145 , H01L2224/32245 , H01L2224/45144 , H01L2224/48145 , H01L2224/48247 , H01L2224/48472 , H01L2224/4911 , H01L2224/73265 , H01L2924/10158 , H01L2924/10253 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00014 , H01L2924/00012
摘要： Gate oxide films, gate electrodes, base regions and emitter regions, which constitute IGBTs, are formed on a semiconductor wafer. A silicon oxide film is formed on the gate electrodes. Further, an emitter electrode is formed thereabove, and a passivation film is formed over the emitter electrode. Thereafter, an internal area of a back surface of the semiconductor wafer is polished to form a protrusion at its outer peripheral portion. Afterwards, an impurity is injected from the back surface of the semiconductor wafer to form a collector region. After a collector electrode is further formed, the semiconductor wafer is mounted on a stage smaller than the internal area and subjected to dicing along scribe areas. Thus, the strength of the semiconductor wafer is held by the protrusion, and cracking or the like of the semiconductor wafer can be reduced owing to the execution of the dicing in the above-described manner.
摘要翻译：构成IGBT的栅极氧化膜，栅极电极，基极区域和发射极区域形成在半导体晶片上。在栅电极上形成氧化硅膜。此外，在上方形成发射电极，在发射电极上形成钝化膜。此后，对半导体晶片的背面的内部区域进行研磨，在其外周部形成突起。之后，从半导体晶片的背面注入杂质，形成集电极区域。在进一步形成集电极之后，将半导体晶片安装在小于内部区域的台上，并沿划线区进行切割。因此，半导体晶片的强度由突起保持，并且由于以上述方式执行切割，可以减小半导体晶片的破裂等。

4. 发明授权

US5539692A Semiconductor memory and method of setting type 失效
标题翻译：半导体存储器和设置方法
公开(公告)号：US5539692A
公开(公告)日：1996-07-23
申请号：US191411
申请日：1994-02-03
申请人： Kazuhiko Kajigaya , Masashi Horiguchi , Yoshinobu Nakagome , Ryoichi Hori , Tetsuro Matsumoto , Masaharu Kubo
发明人： Kazuhiko Kajigaya , Masashi Horiguchi , Yoshinobu Nakagome , Ryoichi Hori , Tetsuro Matsumoto , Masaharu Kubo
IPC分类号： G11C11/401 , G06F11/00 , G11C5/00 , G11C7/10 , G11C29/44 , H01L27/10 , G11C7/00
CPC分类号： G11C29/44 , G06F11/006 , G11C7/1045
摘要： A semiconductor chip is provided with a function selection circuit for selecting memory functions according to the information stored in nonvolatile memory elements is sealed in a package, and the memory functions are set finally by writing the nonvolatile memory element in that state or in a state in which the semiconductor chip is mounted on a board. By setting the type of a semiconductor memory according to the above procedure, the process from the wafer process up to the assembling step can be made common, and hence the mass-productibity and the production control can be facilitated. Semiconductor memories having memory functions conforming to user specifications can be provided in a short time.
摘要翻译：半导体芯片设置有用于根据存储在非易失性存储器元件中的信息来选择存储器功能的功能选择电路，该存储器功能被封装在封装中，并且最终通过将该非易失性存储元件写入该状态或以该状态半导体芯片安装在板上。通过根据上述步骤设置半导体存储器的类型，可以使从晶片处理到组装步骤的过程是共同的，因此可以促进大规模生产和生产控制。可以在短时间内提供具有符合用户规格的记忆功能的半导体存储器。

5. 发明授权

US4672586A Semiconductor memory having circuit effecting refresh on variable cycles 失效
标题翻译：具有电路的半导体存储器在可变周期上进行刷新
公开(公告)号：US4672586A
公开(公告)日：1987-06-09
申请号：US617919
申请日：1984-06-06
申请人： Katsuhiro Shimohigashi , Masaharu Kubo , Katsuki Miyauchi , Toshiaki Masuhara , Osamu Minato
发明人： Katsuhiro Shimohigashi , Masaharu Kubo , Katsuki Miyauchi , Toshiaki Masuhara , Osamu Minato
IPC分类号： G11C11/401 , G11C5/14 , G11C11/406 , G11C11/4072 , G11C11/4074 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L29/788 , H01L29/792 , G11C11/40
CPC分类号： G11C11/406 , G11C11/4072 , G11C11/4074 , G11C5/141
摘要： A semiconductor memory using a dynamic memory device, wherein a battery supplies a power source voltage and a substrate bias voltage when the memory is cut off from an external device, and a refresh control circuit changes in refresh timing of the memory device in accordance with the leakage current of the memory device. The power consumption of the memory can thus be reduced and the data can be kept for an extended period without an external power source.

6. 发明授权

US4451841A Semiconductor device with multi-layered electrodes 失效
标题翻译：具有多层电极的半导体器件
公开(公告)号：US4451841A
公开(公告)日：1984-05-29
申请号：US225268
申请日：1981-01-15
申请人： Ryoichi Hori , Masaharu Kubo , Norikazu Hashimoto , Shigeru Nishimatsu , Kiyoo Itoh
发明人： Ryoichi Hori , Masaharu Kubo , Norikazu Hashimoto , Shigeru Nishimatsu , Kiyoo Itoh
IPC分类号： H01L27/10 , H01L21/3213 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L27/108 , H01L27/115 , H01L29/78 , H01L27/02 , H01L29/04 , H01L29/34
CPC分类号： H01L27/10844 , H01L21/76877 , H01L21/76897 , H01L27/115
摘要： A first semiconductor circuit element including a first electrode is formed on a semiconductor substrate, an inter-layer insulating layer for insulating the first electrode is formed on the first electrode, and a first penetrating opening is provided in a part of the inter-layer insulating layer.Subsequently, a step of forming a second semiconductor circuit element is carried out, this step including a step of forming a second electrode so that at least a part thereof may overlie the inter-layer insulating layer at an area other than the first penetrating opening. Further, a subsidiary interconnection conductive layer is buried into the first opening. Another insulating layer is formed on the structure thus formed, whereupon second and third penetrating openings are respectively provided in the insulating layer over the second electrode and the interconnection subsidiary conductive layer.First and second interconnection conductors are respectively buried into the second and third penetrating openings. The first electrode is conductively connected with the second interconnection conductor in the third opening via the subsidiary interconnection conductive layer in the first opening. The second electrode is conductively connected with the first interconnection conductor in the second opening.
摘要翻译：包括第一电极的第一半导体电路元件形成在半导体衬底上，在第一电极上形成用于绝缘第一电极的层间绝缘层，并且第一穿透开口设置在层间绝缘体的一部分中层。随后，执行形成第二半导体电路元件的步骤，该步骤包括形成第二电极的步骤，使得其至少一部分可以覆盖除了第一穿透开口之外的区域的层间绝缘层。此外，辅助互连导电层被埋入第一开口中。在由此形成的结构上形成另一绝缘层，由此在第二电极和互连副导电层上的绝缘层中分别设置第二和第三穿透开口。第一和第二互连导体分别埋入第二和第三穿透开口中。第一电极通过第一开口中的辅助互连导电层与第三开口中的第二互连导体导电连接。第二电极与第二开口中的第一互连导体导电连接。

7. 发明授权

US4277799A Color solid-state imaging device 失效
标题翻译：彩色固态成像装置
公开(公告)号：US4277799A
公开(公告)日：1981-07-07
申请号：US923982
申请日：1978-07-12
申请人： Norio Koike , Iwao Takemoto , Masaharu Kubo , Kazuhiro Sato , Shusaku Nagahara
发明人： Norio Koike , Iwao Takemoto , Masaharu Kubo , Kazuhiro Sato , Shusaku Nagahara
IPC分类号： H01L27/146 , H04N5/335 , H04N5/341 , H04N5/357 , H04N5/372 , H04N5/374 , H04N9/04 , H04N9/07
CPC分类号： H01L27/14643 , H01L27/14645 , H04N3/1512 , H04N9/045
摘要： A color solid-state imaging device is provided with a plurality of signal output lines for reading out signals derived from photoelectric conversion elements which form picture elements for red, green, and blue lights arranged in, for example, a checkered pattern.
摘要翻译：彩色固态成像装置设置有多条信号输出线，用于读出从形成例如格子图案的红色，绿色和蓝色光的图像元素的光电转换元件导出的信号。

8. 发明授权

US4268845A Solid-state imaging device 失效
标题翻译：固态成像装置
公开(公告)号：US4268845A
公开(公告)日：1981-05-19
申请号：US96683
申请日：1979-11-23
申请人： Norio Koike , Shoji Hanamura , Masaharu Kubo
发明人： Norio Koike , Shoji Hanamura , Masaharu Kubo
IPC分类号： H01L27/146 , H04N5/335 , H04N5/367 , H04N5/372 , H04N5/374 , H01L27/14
CPC分类号： H01L27/14643 , H04N5/2173
摘要： A solid-state imaging device of a picture element construction made up of photodiodes consisting of an N-type semiconductor substrate, a P-type well region formed in the main surface of said semiconductor substrate, and an N-type region formed in said well region, and vertical switching insulated-gate field effect transistors which utilize said N-type region as either the source or the drain, characterized in that a video voltage is applied to said substrate.
摘要翻译：由N型半导体衬底，形成在所述半导体衬底的主表面中的P型阱区和形成在所述阱中的N型区组成的光电二极管构成的像素结构的固体摄像器件区域和垂直开关绝缘栅场效应晶体管，其利用所述N型区域作为源极或漏极，其特征在于，将视频电压施加到所述衬底。

9. 发明授权

US4212034A Solid-state image pickup device 失效
标题翻译：固态图像拾取装置
公开(公告)号：US4212034A
公开(公告)日：1980-07-08
申请号：US931967
申请日：1978-08-08
申请人： Norio Kokie , Masaharu Kubo , Shusaku Nagahara
发明人： Norio Kokie , Masaharu Kubo , Shusaku Nagahara
IPC分类号： H04N3/14 , H04N5/335 , H04N5/341 , H04N5/347 , H04N5/374
CPC分类号： H04N3/1512
摘要： A solid-state image pickup device has a plurality of photoelectric conversion elements arranged in a two-dimensional pattern, to which horizontal and vertical switches are coupled for selecting the photoelectric conversion elements; horizontal and vertical scanning circuitry for turning the switches "on" and "off" are integrated on the same semiconductor substrate. In order to detect an image with low capacitive lag and high resolution power, the required minimum number (four) of switching elements, adapted to turn respective fields "on" and "off" in a predetermined combination, are connected to an output terminal of each of the unit circuits which constitute the vertical scanning circuit. Using an output scanning pulse from the vertical scanning circuit and a field pulse, interlaced scanning in which two row lines are simultaneously selected in one of the combinations differing for the respective fields is executed so as to derive an optical image through the vertical switches.
摘要翻译：固态图像拾取装置具有以二维图案布置的多个光电转换元件，水平和垂直开关耦合到该光电转换元件用于选择光电转换元件; 将开关“开”和“关”的水平和垂直扫描电路集成在同一半导体衬底上。为了检测具有低电容滞后和高分辨率功率的图像，适于将预定组合中的各个场“开”和“关”的所需最小数量（4个）连接到开关元件的输出端每个单元电路构成垂直扫描电路。使用来自垂直扫描电路的输出扫描脉冲和场脉冲，执行其中以对于各个场不同的组合中的一个同时选择两条行线的隔行扫描，以便通过垂直开关导出光学图像。

10. 发明授权

US4032952A Bulk charge transfer semiconductor device 失效
标题翻译：大容量充电传输半导体器件
公开(公告)号：US4032952A
公开(公告)日：1977-06-28
申请号：US347426
申请日：1973-04-03
申请人： Shinya Ohba , Iwao Takemoto , Masaharu Kubo
发明人： Shinya Ohba , Iwao Takemoto , Masaharu Kubo
IPC分类号： H01L29/10 , H01L29/768 , H01L
CPC分类号： H01L29/7685 , H01L29/1062 , H01L29/76833 , H01L29/76841 , Y10S148/08
摘要： In a charge transfer semiconductor device majority carriers are transferred within a semiconductor body on a substrate from means for introducing majority carriers to means for detecting transferred majority carriers by applying pulsed voltages to a series of electrodes disposed on an insulating layer which is disposed on one surface of the semiconductor body between the introducing means and the detecting means. Depletion regions are formed within the semiconductor body, so that one end of a depletion region below one electrode reaches the substrate and another end of a depletion region below an electrode next to the one electrode does not reach the substrate, whereby majority carriers below the one electrode are pushed out below the next electrode.

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