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1. 发明授权

US07198962B2 Semiconductor device and manufacturing method thereof including a probe test step and a burn-in test step 失效
标题翻译：半导体器件及其制造方法，包括探针测试步骤和老化测试步骤
公开(公告)号：US07198962B2
公开(公告)日：2007-04-03
申请号：US10411283
申请日：2003-04-11
申请人： Ryuji Kohno , Tetsuo Kumazawa , Makoto Kitano , Akihiko Ariga , Yuji Wada , Naoto Ban , Shuji Shibuya , Yasuhiro Motoyama , Kunio Matsumoto , Susumu Kasukabe , Terutaka Mori , Hidetaka Shigi , Takayoshi Watanabe
发明人： Ryuji Kohno , Tetsuo Kumazawa , Makoto Kitano , Akihiko Ariga , Yuji Wada , Naoto Ban , Shuji Shibuya , Yasuhiro Motoyama , Kunio Matsumoto , Susumu Kasukabe , Terutaka Mori , Hidetaka Shigi , Takayoshi Watanabe
IPC分类号： G01R31/26 , H01L21/66 , H01L21/00 , H01L21/48
CPC分类号： G01R3/00 , G01R1/0735
摘要： Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.
摘要翻译：即使当大量区域中的多个探针通过将设置在膜中的探针压迫到晶片而将压力负载施加到压力构件的平面的多个位置时，负载的分散也可以保持在容许范围内在作为半导体器件制造步骤之一的探针测试步骤/老化测试步骤中与晶片相对的一侧。因此，可以提供通过同时探测大量集成电路或大尺寸集成电路来提高半导体器件的可靠性和生产率的半导体器件及其制造方法。

2. 发明授权

US06828810B2 Semiconductor device testing apparatus and method for manufacturing the same 失效
标题翻译：半导体器件测试装置及其制造方法
公开(公告)号：US06828810B2
公开(公告)日：2004-12-07
申请号：US10207145
申请日：2002-07-30
申请人： Masatoshi Kanamaru , Yoshishige Endo , Takanori Aono , Ryuji Kohno , Hiroya Shimizu , Naoto Ban , Hideyuki Aoki
发明人： Masatoshi Kanamaru , Yoshishige Endo , Takanori Aono , Ryuji Kohno , Hiroya Shimizu , Naoto Ban , Hideyuki Aoki
IPC分类号： G01R3102
CPC分类号： G01R1/0466
摘要： A semiconductor device testing apparatus is realized, which allows contactors to be positioned throughout the wafer surface highly accurately for uniform contact, testing a large-sized wafer, and cost reduction. A plurality of divided contactor blocks is formed with a positioning groove. The groove is used to position the plurality of contactor blocks with a positioning frame. Because the contactor blocks are divided into plurals, it is less likely that a partial surface distortion affects other portions to impair surface flatness as compared with the case where a plurality of non-divided contactors is formed integrally, and the plurality of contactor blocks can be brought into contact with a wafer to be tested uniformly. Additionally, even though abnormality is generated in a part of the contactor blocks, only the part of the contactor blocks is replaced. Therefore, replacement costs can be reduced as compared with the case where a plurality of non-divided contactors is formed integrally.
摘要翻译：实现半导体器件测试装置，其允许接触器高精度地定位在整个晶片表面，用于均匀接触，测试大尺寸晶片以及降低成本。多个分开的接触器块形成有定位槽。凹槽用于定位具有定位框架的多个接触器块。由于接触器块被分成多个，与多个非分隔接触器形成为一体的情况相比，部分表面变形对其他部分的影响较小可能损害表面平坦度，并且多个接触器块可以与待测试的晶片均匀接触。此外，即使在接触器块的一部分中产生异常，仅更换接触器块的一部分。因此，与多个非分割接触器一体形成的情况相比，可以降低更换成本。

3. 发明授权

US06566150B2 Semiconductor device and manufacturing method thereof including a probe test step and a burn-in test step 失效
公开(公告)号：US06566150B2
公开(公告)日：2003-05-20
申请号：US10171695
申请日：2002-06-17
申请人： Ryuji Kohno , Tetsuo Kumazawa , Makoto Kitano , Akihiko Ariga , Yuji Wada , Naoto Ban , Shuji Shibuya , Yasuhiro Motoyama , Kunio Matsumoto , Susumu Kasukabe , Terutaka Mori , Hidetaka Shigi , Takayoshi Watanabe
发明人： Ryuji Kohno , Tetsuo Kumazawa , Makoto Kitano , Akihiko Ariga , Yuji Wada , Naoto Ban , Shuji Shibuya , Yasuhiro Motoyama , Kunio Matsumoto , Susumu Kasukabe , Terutaka Mori , Hidetaka Shigi , Takayoshi Watanabe
IPC分类号： G01R3126
CPC分类号： G01R3/00 , G01R1/0735
摘要： Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.

4. 发明授权

US06566149B1 Method for manufacturing substrate for inspecting semiconductor device 失效
标题翻译：用于检查半导体器件的衬底的制造方法
公开(公告)号：US06566149B1
公开(公告)日：2003-05-20
申请号：US09787250
申请日：2001-03-16
申请人： Masatoshi Kanamaru , Atsushi Hosogane , Yoshihige Endou , Ryuji Kouno , Hideo Miura , Shinji Tanaka , Hiroyuki Ohta , Akihiko Ariga , Naoto Ban , Hideyuki Aoki
发明人： Masatoshi Kanamaru , Atsushi Hosogane , Yoshihige Endou , Ryuji Kouno , Hideo Miura , Shinji Tanaka , Hiroyuki Ohta , Akihiko Ariga , Naoto Ban , Hideyuki Aoki
IPC分类号： G01R3126
CPC分类号： G01R3/00
摘要： For an inspection tray, a silicon substrate including a beam or a diaphragm, a probe and wiring is used. To highly accurately position a chip to be inspected, a second substrate for alignment is disposed on the substrate. To position the probe having wiring disposed on the first substrate and the electrode pad of the chip to be inspected, a projection or a groove is formed in each of both substrates. Preferably, the projection or groove should be formed by silicon anisotorpic etching to have a (111) crystal surface. As another machining method, dry etching can be used for machining the positioning projection or groove. By using an inductively coupled plasma-reactive ion etching (ICP-RIE) device for the dry etching, a vertical column or groove can be easily machined.
摘要翻译：对于检查托盘，使用包括梁或隔膜，探针和布线的硅基板。为了高精度地定位待检查的芯片，在基板上设置用于对准的第二基板。为了定位具有设置在第一基板上的布线的探针和要检查的芯片的电极焊盘，在两个基板中的每一个中形成突起或凹槽。优选地，突起或凹槽应由硅各向异性蚀刻形成以具有（111）晶体表面。作为另一种加工方法，可以使用干蚀刻来加工定位突起或凹槽。通过使用用于干蚀刻的电感耦合等离子体反应离子蚀刻（ICP-RIE）装置，可以容易地加工垂直的柱或槽。

5. 发明授权

US06511857B1 Process for manufacturing semiconductor device 有权
标题翻译：半导体器件制造工艺
公开(公告)号：US06511857B1
公开(公告)日：2003-01-28
申请号：US09646511
申请日：2001-01-12
申请人： Ryuji Kono , Makoto Kitano , Hideo Miura , Hiroyuki Ota , Yoshishige Endo , Takeshi Harada , Masatoshi Kanamaru , Teruhisa Akashi , Atsushi Hosogane , Akihiko Ariga , Naoto Ban
发明人： Ryuji Kono , Makoto Kitano , Hideo Miura , Hiroyuki Ota , Yoshishige Endo , Takeshi Harada , Masatoshi Kanamaru , Teruhisa Akashi , Atsushi Hosogane , Akihiko Ariga , Naoto Ban
IPC分类号： H01L2100
CPC分类号： G01R1/07314 , G01R1/06744 , G01R3/00 , G01R31/2863
摘要： In an electric characteristic testing process corresponding to a process of the semiconductor apparatus manufacturing processes, in order to test a large area of the electrode pad of the body to be tested in a lump, an electric characteristic testing is performed by pressing a testing structure provided with electrically independent projections having a number equal to a number of conductor portions to be tested formed on an area to be tested of a body to be tested to the body to be tested.
摘要翻译：在与半导体装置制造工序相对应的电气特性测试过程中，为了一体地测试待测试体的电极焊盘的大面积面积，通过按压所提供的测试结构来进行电特性测试具有电数独立的突起，其数量等于要测试的被测体的待测试区域上待测试的导体部分的数量。

6. 发明授权

US06496023B1 Semiconductor-device inspecting apparatus and a method for manufacturing the same 失效
标题翻译：半导体装置检查装置及其制造方法
公开(公告)号：US06496023B1
公开(公告)日：2002-12-17
申请号：US09722484
申请日：2000-11-28
申请人： Masatoshi Kanamaru , Yoshishige Endo , Takanorr Aono , Ryuji Kohno , Toshio Miyatake , Hideyuki Aoki , Naoto Ban
发明人： Masatoshi Kanamaru , Yoshishige Endo , Takanorr Aono , Ryuji Kohno , Toshio Miyatake , Hideyuki Aoki , Naoto Ban
IPC分类号： G01R3102
CPC分类号： G01R1/07357 , Y10S977/874
摘要： A structure is provided such that a plural cantilevers are formed on a first board formed of silicon, probes are respectively formed on the individual cantilevers at positions each offset perpendicularly to a longitudinal center line of the cantilever, and wiring connected continuously from each probe to a secondary electrode pad portion through an insulating layer. A structure is alternatively adopted such that by using a both-ends supported beam formed of silicon as the beam, each probe is formed at a position offset toward a supported portion side of the both-ends supported beam.
摘要翻译：提供一种结构，使得在由硅形成的第一板上形成多个悬臂，在各个悬臂分别在垂直于悬臂的纵向中心线偏移的位置处形成探针，并且从每个探针连续连接到每个探针次级电极焊盘部分穿过绝缘层。可替代地采用结构，使得通过使用由硅形成的两端支撑梁作为梁，每个探针形成在朝向两端支撑梁的支撑部分侧偏移的位置。

7. 发明授权

US06479305B2 Semiconductor device manufacturing method 失效
标题翻译：半导体器件制造方法
公开(公告)号：US06479305B2
公开(公告)日：2002-11-12
申请号：US09396732
申请日：1999-09-15
申请人： Ryuji Kono , Akihiko Ariga , Hideyuki Aoki , Hiroyuki Ohta , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Shinji Tanaka , Naoto Ban , Hideo Miura
发明人： Ryuji Kono , Akihiko Ariga , Hideyuki Aoki , Hiroyuki Ohta , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Shinji Tanaka , Naoto Ban , Hideo Miura
IPC分类号： H01L2166
CPC分类号： H01L21/6836 , H01L22/20 , H01L2221/68327 , H01L2924/0002 , H01L2924/014 , H01L2924/00
摘要： Semiconductor device chips manufacturing and inspecting method is disclosed in which a semiconductor wafer is cut into individual LSI chips. The LSI chips are rearranged and integrated into a predetermined number. The cut LSI chips are integrated in a jig having openings with a size commensurate with the dimensions of the LSI chip. At least one part of the jig having such openings has a coefficient of thermal expansion that is approximately equal to that of the LSI chips. The integrated predetermined number of chips are subjected to an inspection process in a subsequent inspection step thereby improving efficiency and reducing cost.
摘要翻译：半导体器件芯片制造和检查方法被公开，其中将半导体晶片切割成单独的LSI芯片。 LSI芯片重新排列并集成为预定数量。切割的LSI芯片集成在具有与LSI芯片的尺寸相当的尺寸的开口的夹具中。具有这种开口的夹具的至少一部分具有与LSI芯片大致相同的热膨胀系数。综合预定数量的芯片在随后的检查步骤中进行检查处理，从而提高效率并降低成本。

8. 发明授权

US06358762B1 Manufacture method for semiconductor inspection apparatus 失效
公开(公告)号：US06358762B1
公开(公告)日：2002-03-19
申请号：US09534302
申请日：2000-03-23
申请人： Ryuji Kohno , Hideo Miura , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Hideyuki Aoki , Naoto Ban
发明人： Ryuji Kohno , Hideo Miura , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Hideyuki Aoki , Naoto Ban
IPC分类号： G01R3126
CPC分类号： H01L22/32 , G01R1/06711 , G01R1/06738 , G01R1/07314 , G01R3/00 , H01L23/13 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes. A method of manufacturing the semiconductor inspection apparatus comprises the steps of forming a cover film on a surface of the silicon substrate and forming a plurality of probes of a polygonal cone shape or a circular cone shape through etching after patterning by photolithography, after the cover film is removed, again forming a cover film on the surface of the silicon substrate and forming a beam or a diaphragm for each probe through etching after patterning by photolithography, after the cover film is removed, again forming a cover film on the surface of the silicon substrate and forming a through hole corresponding to the probe through etching after patterning by photolithography, and after the cover film is removed, forming an insulating film on the surface of the silicon substrate, forming a metal film on a surface of the insulating film, and forming a wiring lead through etching after patterning by photolithography.

9. 发明授权

US5532909A Reflector for a vehicular lamp and method of producing a die therefor 失效
标题翻译：一种用于车灯的反射器及其制造方法
公开(公告)号：US5532909A
公开(公告)日：1996-07-02
申请号：US288388
申请日：1994-08-03
申请人： Naoto Ban , Hiroshi Kawashima
发明人： Naoto Ban , Hiroshi Kawashima
IPC分类号： F21S8/10 , F21V7/00 , F21V7/04 , F21V7/09 , G02B5/10 , B60Q1/30
CPC分类号： F21S48/1352 , F21V7/04 , F21V7/09
摘要： A lamp reflector for a lamp that conforms to a vehicle body shape and method of producing such reflector, including a die therefor. The lamp reflector comprises a plurality of reflecting sections disposed about an optical axis of the lamp. Significant differences in light distribution at the boundaries between the reflecting sections are avoided by using a fundamental surface K of a reflecting surface 3 that may be generated as a free surface so as to conform to a vehicle body shape. After a reference curve is set on the fundamental surface K, several points P, P, . . . are specified on the reference curve. A very small reflecting surface R is determined at the point P according to the law of reflection so that a ray emitted from a light source and made incident on the point P is reflected to become a ray in parallel with the optical axis. Then, a tangential plane T of the fundamental surface at the point P is determined, and an outer product W of a normal vector N.sub.-- T of the tangential plane T and a normal vector N.sub.13 R of the very small reflecting surface R is calculated. A closed curve is generated by performing vector control in which the outer product W is employed as its tangential vector at each reflection point P around the optical axis, and connecting the tangential vectors by spline approximation.
摘要翻译：一种符合车体形状的灯的灯反射器和制造这种反射器的方法，包括一个管芯。灯反射器包括围绕灯的光轴设置的多个反射部分。通过使用可以作为自由表面产生的符合车身形状的反射面3的基面K来避免反射部分之间的边界处的光分布的显着差异。在基面K上设置参考曲线后，可以将几个点P，P，。。在参考曲线上指定。根据反射定律在点P处确定非常小的反射表面R，使得从光源发射并入射到点P上的光线被反射成与光轴平行的射线。然后，确定点P处的基面的切线面T，并计算切线面T的法线矢量N-T的外积W和非常小的反射面R的法线向量N13R。通过执行矢量控制来生成闭合曲线，其中使用外积W作为围绕光轴的每个反射点P处的切向矢量，并且通过样条近似来连接切向矢量。

10. 发明授权

US06864695B2 Semiconductor device testing apparatus and semiconductor device manufacturing method using it 失效
标题翻译：半导体器件测试装置及其使用的半导体器件制造方法
公开(公告)号：US06864695B2
公开(公告)日：2005-03-08
申请号：US09925375
申请日：2001-08-10
申请人： Ryuji Kohno , Hideo Miura , Masatoshi Kanamaru , Hiroya Shimizu , Naoto Ban
发明人： Ryuji Kohno , Hideo Miura , Masatoshi Kanamaru , Hiroya Shimizu , Naoto Ban
IPC分类号： G01R1/073 , G01R3/00 , G01R31/28 , H01L21/66 , G01R31/02
CPC分类号： G01R3/00 , G01R1/07357
摘要： Since each wiring line is formed on one surface of the associated beam at a prescribed width over the entire length of the beam, the beam has the same sectional shape taken in the width direction at any point along an arbitrary longitudinal direction of the beam. As a result, the second moment of area, which is determined by the shapes of the beam and the wiring line, is uniform. This prevents a problem of the curvature of a beam varying locally when the beam is bent by a prescribed amount due to contact of the probe with a pad of a subject body. This, in turn, prevents local concentration of stress in the beams and thereby prevents breakage of the beam. Therefore, the probe structure can be miniaturized while the strength of the beams is kept at a required level, whereby a semiconductor device testing apparatus capable of accommodating many probes can be realized.
摘要翻译：由于每个布线在波束的整个长度上以规定的宽度形成在相关联的光束的一个表面上，所以光束在沿着光束的任意纵向方向的任何点处具有在宽度方向上取下的截面形状。结果，由光束和布线的形状确定的面积的第二时刻是均匀的。这防止了当由于探针与被检体的垫接触而使光束弯曲预定量时局部变化的光束曲率的问题。这反过来又防止梁中的局部应力集中，从而防止梁的断裂。因此，能够将光束的强度保持在所要求的水平，能够使探头结构小型化，能够实现容纳多个探针的半导体装置的测试装置。

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