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1. 发明申请

US20090209053A1 CONNECTION DEVICE AND TEST SYSTEM 审中-公开
标题翻译：连接装置和测试系统
公开(公告)号：US20090209053A1
公开(公告)日：2009-08-20
申请号：US12408000
申请日：2009-03-20
申请人： Susumu KASUKABE , Terutaka Mori , Akihiko Ariga , Hidetaka Shigi , Takayoshi Watanabe , Ryuji Kono
发明人： Susumu KASUKABE , Terutaka Mori , Akihiko Ariga , Hidetaka Shigi , Takayoshi Watanabe , Ryuji Kono
IPC分类号： H01L21/66
CPC分类号： G01R31/2889 , G01R1/06744 , G01R1/06772 , G01R1/0735 , G01R3/00 , G01R31/2863
摘要： To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multilayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multilayer film. A clamping member is provided on the frame to make the multilayer film project out to eliminate slack in the multilayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member. A compliance mechanism is provided so that the contact terminal group of the tip surface is arrayed in parallel with the electrode group terminal surface, so that the tips of the contact terminals contact the surface of the electrodes with an equal pressure.
摘要翻译：为了在连接装置和测试器之间实现电信号的高速交换，提供支撑构件以支撑连接装置，多个尖端接触端子排列在探测侧的区域中，提供多层膜，其具有电连接到接触端子的多个引出线和包围绝缘层的接地层，并且框架被夹持在多层膜的后侧。在框架上设置夹紧构件以使多层膜突出以消除多层膜中的松弛。提供接触压力装置，用于使接触端子的尖端以预定的从支撑构件到夹紧构件的接触压力接触每个电极。提供了一种符合机构，使得尖端表面的接触端子组与电极组端子表面平行地排列，使得接触端子的尖端以相等的压力接触电极的表面。

2. 发明授权

US07119362B2 Method of manufacturing semiconductor apparatus 有权
公开(公告)号：US07119362B2
公开(公告)日：2006-10-10
申请号：US10326663
申请日：2002-12-23
申请人： Ryuji Kono , Makoto Kitano , Hideo Miura , Hiroyuki Ota , Yoshishige Endo , Takeshi Harada , Masatoshi Kanamaru , Teruhisa Akashi , Atsushi Hosogane , Akihiko Ariga , Naoto Ban
发明人： Ryuji Kono , Makoto Kitano , Hideo Miura , Hiroyuki Ota , Yoshishige Endo , Takeshi Harada , Masatoshi Kanamaru , Teruhisa Akashi , Atsushi Hosogane , Akihiko Ariga , Naoto Ban
IPC分类号： H01L23/58
CPC分类号： G01R1/07314 , G01R1/06744 , G01R3/00 , G01R31/2863
摘要： In an electric characteristic testing process corresponding to a process of the semiconductor apparatus manufacturing processes, in order to test a large area of the electrode pad of the body to be tested in a lump, an electric characteristic testing is performed by pressing a testing structure provided with electrically independent projections having a number equal to a number of conductor portions to be tested formed on an area to be tested of a body to be tested to the body to be tested.

3. 发明授权

US06573112B2 Semiconductor device manufacturing method 失效
公开(公告)号：US06573112B2
公开(公告)日：2003-06-03
申请号：US10238690
申请日：2002-09-11
申请人： Ryuji Kono , Akihiko Ariga , Hideyuki Aoki , Hiroyuki Ohta , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Shinji Tanaka , Naoto Ban , Hideo Miura
发明人： Ryuji Kono , Akihiko Ariga , Hideyuki Aoki , Hiroyuki Ohta , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Shinji Tanaka , Naoto Ban , Hideo Miura
IPC分类号： H01L2166
CPC分类号： H01L21/6836 , H01L22/20 , H01L2221/68327 , H01L2924/0002 , H01L2924/014 , H01L2924/00
摘要： Semiconductor device chips manufacturing and inspecting method is disclosed in which a semiconductor wafer is cut into individual LSI chips. The LSI chips are rearranged and integrated into a predetermined number. The cut LSI chips are integrated in a jig having openings with a size commensurate with the dimensions of the LSI chip. At least one part of the jig having such openings has a coefficient of thermal expansion that is approximately equal to that of the LSI chips. The integrated predetermined number of chips are subjected to an inspection process in a subsequent inspection step thereby improving efficiency and reducing cost.

4. 发明授权

US06455335B1 Semiconductor device and manufacturing method thereof including a probe test step and a burn-in test step 失效
公开(公告)号：US06455335B1
公开(公告)日：2002-09-24
申请号：US09653624
申请日：2000-08-31
申请人： Ryuji Kohno , Tetsuo Kumazawa , Makoto Kitano , Akihiko Ariga , Yuji Wada , Naoto Ban , Shuji Shibuya , Yasuhiro Motoyama , Kunio Matsumoto , Susumu Kasukabe , Terutaka Mori , Hidetaka Shigi , Takayoshi Watanabe
发明人： Ryuji Kohno , Tetsuo Kumazawa , Makoto Kitano , Akihiko Ariga , Yuji Wada , Naoto Ban , Shuji Shibuya , Yasuhiro Motoyama , Kunio Matsumoto , Susumu Kasukabe , Terutaka Mori , Hidetaka Shigi , Takayoshi Watanabe
IPC分类号： G01R3126
CPC分类号： G01R3/00 , G01R1/0735
摘要： Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.

5. 发明申请

US20080009082A1 CONNECTION DEVICE AND TEST SYSTEM 失效
标题翻译：连接装置和测试系统
公开(公告)号：US20080009082A1
公开(公告)日：2008-01-10
申请号：US11853979
申请日：2007-09-12
申请人： Susumu Kasukabe , Terutaka Mori , Akihiko Ariga , Hidetaka Shigi , Takayoshi Watanabe , Ryuji Kono
发明人： Susumu Kasukabe , Terutaka Mori , Akihiko Ariga , Hidetaka Shigi , Takayoshi Watanabe , Ryuji Kono
IPC分类号： H01L21/66
CPC分类号： G01R31/2889 , G01R1/06744 , G01R1/06772 , G01R1/0735 , G01R3/00 , G01R31/2863
摘要： To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member. A compliance mechanism is provided so that the contact terminal group of the tip surface is arrayed in parallel with the electrode group terminal surface, so that the tips of the contact terminals contact the surface of the electrodes with an equal pressure.
摘要翻译：为了在连接装置和测试器之间实现电信号的高速交换，提供了一种用于支撑连接装置的支撑构件，多个尖端接触端子被排列在探测侧的区域中，提供了一种多层膜，其具有电连接到接触端子的多个引出线和包围绝缘层的接地层，并且框架被夹持在多人膜的后侧。夹持构件设置在框架上以使多人影片投射出来以消除多人影片中的松弛。提供接触压力装置，用于使接触端子的尖端以预定的从支撑构件到夹紧构件的接触压力接触每个电极。提供了一种符合机构，使得尖端表面的接触端子组与电极组端子表面平行地排列，使得接触端子的尖端以相等的压力接触电极的表面。

6. 发明授权

US06507204B1 Semiconductor testing equipment with probe formed on a cantilever of a substrate 失效
标题翻译：具有探针的半导体测试设备形成在基板的悬臂上
公开(公告)号：US06507204B1
公开(公告)日：2003-01-14
申请号：US09522477
申请日：2000-03-09
申请人： Masatoshi Kanamaru , Yoshishige Endo , Atsushi Hosogane , Tatsuya Nagata , Ryuji Kohno , Hideyuki Aoki , Akihiko Ariga
发明人： Masatoshi Kanamaru , Yoshishige Endo , Atsushi Hosogane , Tatsuya Nagata , Ryuji Kohno , Hideyuki Aoki , Akihiko Ariga
IPC分类号： G01R3102
CPC分类号： G01R1/06733 , G01R1/06727 , G01R1/06738 , G01R1/06761 , G01R1/06772 , G01R1/07342 , G01R3/00
摘要： The conventional semiconductor element testing equipment is arranged to position each probe accurately and need a burdensome operation for fixing, and includes only a limited number of electrode pads and chips to be tested at a batch. An equipment for testing a semiconductor element is arranged to keep each of electrode pads formed on a semiconductor element to be tested in direct contact with each of probes formed on a first substrate composed of silicon, one of electric connecting substrates disposed in the equipment. On the first substrate, each probe is formed on a cantilever and a wire is routed from a tip of each probe along a tip of the cantilever to the electrode pad formed on an opposite surface to the probe forming surface through an insulating layer.
摘要翻译：常规的半导体元件测试设备被布置成准确地定位每个探针，并且需要用于固定的繁重的操作，并且仅包括有限数量的待批测试的电极焊盘和芯片。布置了用于测试半导体元件的设备，以使每个形成在要测试的半导体元件上的电极焊盘与形成在由设置在设备中的电连接基板之一的硅构成的第一基板上形成的每个探针直接接触。在第一基板上，每个探针形成在悬臂上，并且从每个探针的尖端沿着悬臂的尖端布线到通过绝缘层与探针形成表面相对的表面上形成的电极焊盘。

7. 发明授权

US07285430B2 Connection device and test system 失效
标题翻译：连接设备和测试系统
公开(公告)号：US07285430B2
公开(公告)日：2007-10-23
申请号：US10873168
申请日：2004-06-23
申请人： Susumu Kasukabe , Terutaka Mori , Akihiko Ariga , Hidetaka Shigi , Takayoshi Watanabe , Ryuji Kono
发明人： Susumu Kasukabe , Terutaka Mori , Akihiko Ariga , Hidetaka Shigi , Takayoshi Watanabe , Ryuji Kono
IPC分类号： G01R31/26
CPC分类号： G01R31/2889 , G01R1/06744 , G01R1/06772 , G01R1/0735 , G01R3/00 , G01R31/2863
摘要： To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member. A compliance mechanism is provided so that the contact terminal group of the tip surface is arrayed in parallel with the electrode group terminal surface, so that the tips of the contact terminals contact the surface of the electrodes with an equal pressure.
摘要翻译：为了在连接装置和测试器之间实现电信号的高速交换，提供了一种用于支撑连接装置的支撑构件，多个尖端接触端子被排列在探测侧的区域中，提供了一种多层膜，其具有电连接到接触端子的多个引出线和包围绝缘层的接地层，并且框架被夹持在多人膜的后侧。夹持构件设置在框架上以使多人影片投射出来以消除多人影片中的松弛。提供接触压力装置，用于使接触端子的尖端以预定的从支撑构件到夹紧构件的接触压力接触每个电极。提供了一种符合机构，使得尖端表面的接触端子组与电极组端子表面平行地排列，使得接触端子的尖端以相等的压力接触电极的表面。

8. 发明授权

US06197603B1 Semiconductor device and manufacturing method thereof including a probe test step and a burn-in test step 失效
标题翻译：半导体器件及其制造方法，包括探针测试步骤和老化测试步骤
公开(公告)号：US06197603B1
公开(公告)日：2001-03-06
申请号：US09157153
申请日：1998-09-18
申请人： Ryuji Kohno , Tetsuo Kumazawa , Makoto Kitano , Akihiko Ariga , Yuji Wada , Naoto Ban , Shuji Shibuya , Yasuhiro Motoyama , Kunio Matsumoto , Susumu Kasukabe , Terutaka Mori , Hidetaka Shigi , Takayoshi Watanabe
发明人： Ryuji Kohno , Tetsuo Kumazawa , Makoto Kitano , Akihiko Ariga , Yuji Wada , Naoto Ban , Shuji Shibuya , Yasuhiro Motoyama , Kunio Matsumoto , Susumu Kasukabe , Terutaka Mori , Hidetaka Shigi , Takayoshi Watanabe
IPC分类号： G01R3126
CPC分类号： G01R3/00 , G01R1/0735
摘要： Dispersion of a load may be kept within a predetermined allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane against a wafer by applying a pressure load to a plurality of places on a plane of the pressure members on the side opposite the wafer in a probe test step, burn-in test step which represent typical semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit at the same time.
摘要翻译：即使当大量区域中的多个探针通过将设置在膜中的探针压在晶片上时，通过将压力负载施加到多个位置的平面上的多个位置，负载的分散也可以保持在预定容限内在探针测试步骤中与晶片相对的一侧的压力构件，代表典型的半导体器件制造步骤的老化测试步骤。因此，可以提供通过同时探测大量集成电路或大尺寸集成电路来提高半导体器件的可靠性和生产率的半导体器件及其制造方法。

9. 发明授权

US07541202B2 Connection device and test system 失效
公开(公告)号：US07541202B2
公开(公告)日：2009-06-02
申请号：US11853979
申请日：2007-09-12
申请人： Susumu Kasukabe , Terutaka Mori , Akihiko Ariga , Hidetaka Shigi , Takayoshi Watanabe , Ryuji Kono
发明人： Susumu Kasukabe , Terutaka Mori , Akihiko Ariga , Hidetaka Shigi , Takayoshi Watanabe , Ryuji Kono
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： G01R31/2889 , G01R1/06744 , G01R1/06772 , G01R1/0735 , G01R3/00 , G01R31/2863
摘要： To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member. A compliance mechanism is provided so that the contact terminal group of the tip surface is arrayed in parallel with the electrode group terminal surface, so that the tips of the contact terminals contact the surface of the electrodes with an equal pressure.

10. 发明授权

US07198962B2 Semiconductor device and manufacturing method thereof including a probe test step and a burn-in test step 失效
标题翻译：半导体器件及其制造方法，包括探针测试步骤和老化测试步骤
公开(公告)号：US07198962B2
公开(公告)日：2007-04-03
申请号：US10411283
申请日：2003-04-11
申请人： Ryuji Kohno , Tetsuo Kumazawa , Makoto Kitano , Akihiko Ariga , Yuji Wada , Naoto Ban , Shuji Shibuya , Yasuhiro Motoyama , Kunio Matsumoto , Susumu Kasukabe , Terutaka Mori , Hidetaka Shigi , Takayoshi Watanabe
发明人： Ryuji Kohno , Tetsuo Kumazawa , Makoto Kitano , Akihiko Ariga , Yuji Wada , Naoto Ban , Shuji Shibuya , Yasuhiro Motoyama , Kunio Matsumoto , Susumu Kasukabe , Terutaka Mori , Hidetaka Shigi , Takayoshi Watanabe
IPC分类号： G01R31/26 , H01L21/66 , H01L21/00 , H01L21/48
CPC分类号： G01R3/00 , G01R1/0735
摘要： Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.
摘要翻译：即使当大量区域中的多个探针通过将设置在膜中的探针压迫到晶片而将压力负载施加到压力构件的平面的多个位置时，负载的分散也可以保持在容许范围内在作为半导体器件制造步骤之一的探针测试步骤/老化测试步骤中与晶片相对的一侧。因此，可以提供通过同时探测大量集成电路或大尺寸集成电路来提高半导体器件的可靠性和生产率的半导体器件及其制造方法。

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