专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050079667A1 Semiconductor device and production method therefor 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050079667A1
公开(公告)日：2005-04-14
申请号：US10503350
申请日：2003-02-05
申请人： Tomio Iwasaki , Norio Ishitsuka , Hideo Miura
发明人： Tomio Iwasaki , Norio Ishitsuka , Hideo Miura
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8244 , H01L21/8247 , H01L27/11 , H01L27/115 , H01L29/49 , H01L29/78 , H01L29/788 , H01L29/792 , H01L21/425 , H01L21/8234 , H01L21/8238 , H01L29/76 , H01L29/94
CPC分类号： H01L29/6659 , H01L21/26513 , H01L29/4925 , H01L29/4983 , H01L29/7833
摘要： A semiconductor device having a high degree of reliability is provided. A second object of the invention is to provide a semiconductor device of high yield. The semiconductor includes a silicon substrate, a gate dielectric film formed on one main surface of the silicon substrate, a gate electrode formed by being stacked on the gate dielectric film and a diffusion layer containing arsenic and phosphorus. Both of the concentration of the highest concentration portion of arsenic and the concentration of the highest concentration portion of phosphorus are each at 1026 atoms/m3 or more and 1027 atoms/m3 or less, and the depth of the highest concentration portion of phosphorus from the surface of the silicon substrate is less than the depth of the highest concentration portion of arsenic.
摘要翻译：提供了具有高可靠性的半导体器件。本发明的第二个目的是提供一种高产率的半导体器件。半导体包括硅衬底，形成在硅衬底的一个主表面上的栅极电介质膜，通过层叠在栅极电介质膜上形成的栅电极和含有砷和磷的扩散层。砷的最高浓度部分的浓度和磷的最高浓度部分的浓度分别为10 26个/ m 3以上且10 27个/ m 3以下，并且来自硅衬底的表面的磷的最高浓度部分的深度小于砷的最高浓度部分的深度。

2. 发明授权

US07141840B2 Semiconductor device and production method therefor 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07141840B2
公开(公告)日：2006-11-28
申请号：US10503350
申请日：2003-02-05
申请人： Tomio Iwasaki , Norio Ishitsuka , Hideo Miura
发明人： Tomio Iwasaki , Norio Ishitsuka , Hideo Miura
IPC分类号： H01L31/112
CPC分类号： H01L29/6659 , H01L21/26513 , H01L29/4925 , H01L29/4983 , H01L29/7833
摘要： A semiconductor device having a high degree of reliability is provided. A second object of the invention is to provide a semiconductor device of high yield. The semiconductor includes a silicon substrate, a gate dielectric film formed on one main surface of the silicon substrate, a gate electrode formed by being stacked on the gate dielectric film and a diffusion layer containing arsenic and phosphorus. Both of the concentration of the highest concentration portion of arsenic and the concentration of the highest concentration portion of phosphorus are each at 1026 atoms/m3 or more and 1027 atoms/m3 or less, and the depth of the highest concentration portion of phosphorus from the surface of the silicon substrate is less than the depth of the highest concentration portion of arsenic.
摘要翻译：提供了具有高可靠性的半导体器件。本发明的第二个目的是提供一种高产率的半导体器件。半导体包括硅衬底，形成在硅衬底的一个主表面上的栅极电介质膜，通过层叠在栅极电介质膜上形成的栅电极和含有砷和磷的扩散层。砷的最高浓度部分的浓度和磷的最高浓度部分的浓度都分别为10 26原子/ m 3以上且10以下 > 27原子/ m 3以下，并且来自硅衬底表面的磷的最高浓度部分的深度小于砷的最高浓度部分的深度。

3. 发明授权

US07084477B2 Semiconductor device and manufacturing method of the same 失效
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07084477B2
公开(公告)日：2006-08-01
申请号：US10600771
申请日：2003-06-23
申请人： Norio Ishitsuka , Tomio Iwasaki , Hiroyuki Ohta , Hideo Miura , Masahito Takahashi , Norio Suzuki , Shuji Ikeda , Hideki Tanaka , Hiroyuki Mima
发明人： Norio Ishitsuka , Tomio Iwasaki , Hiroyuki Ohta , Hideo Miura , Masahito Takahashi , Norio Suzuki , Shuji Ikeda , Hideki Tanaka , Hiroyuki Mima
IPC分类号： H01L29/00
CPC分类号： H01L27/11526 , H01L21/28123 , H01L21/76224 , H01L21/823481 , H01L27/105 , H01L27/11546
摘要： To suppress defects occurred in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.
摘要翻译：为了抑制在半导体衬底中发生的缺陷，半导体器件通过具有：半导体衬底; 具有形成在所述半导体衬底中的沟槽的元件隔离区域和嵌入所述沟槽中的嵌入绝缘膜; 形成在元件隔离区域附近形成的有源区，其中形成栅极绝缘膜并在栅极绝缘膜上形成栅电极; 以及形成为使得栅电极的至少一部分位于元件隔离区域上的区域，以及在栅电极为第一元件隔离区域的嵌入绝缘膜的上侧的第一边缘表面定位在位于绝缘膜的第二边缘表面上方的第二元件隔离区域中，栅极电极膜未被定位。

4. 发明申请

US20060214254A1 Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20060214254A1
公开(公告)日：2006-09-28
申请号：US11443226
申请日：2006-05-31
申请人： Norio Ishitsuka , Tomio Iwasaki , Hiroyuki Ohta , Hideo Miura , Masahito Takahashi , Norio Suzuki , Shuji Ikeda , Hideki Tanaka , Hiroyuki Mima
发明人： Norio Ishitsuka , Tomio Iwasaki , Hiroyuki Ohta , Hideo Miura , Masahito Takahashi , Norio Suzuki , Shuji Ikeda , Hideki Tanaka , Hiroyuki Mima
IPC分类号： H01L29/00
CPC分类号： H01L27/11526 , H01L21/28123 , H01L21/76224 , H01L21/823481 , H01L27/105 , H01L27/11546
摘要： To suppress occurrence of defects in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.
摘要翻译：为了抑制半导体衬底中的缺陷的发生，半导体器件通过具有：半导体衬底; 具有形成在所述半导体衬底中的沟槽的元件隔离区域和嵌入所述沟槽中的嵌入绝缘膜; 形成在元件隔离区域附近形成的有源区，其中形成栅极绝缘膜并在栅极绝缘膜上形成栅电极; 以及形成为使得栅电极的至少一部分位于元件隔离区域上的区域，以及在栅电极为第一元件隔离区域的嵌入绝缘膜的上侧的第一边缘表面定位在位于绝缘膜的第二边缘表面上方的第二元件隔离区域中，栅极电极膜未被定位。

5. 发明申请

US20080188043A1 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20080188043A1
公开(公告)日：2008-08-07
申请号：US12005444
申请日：2007-12-26
申请人： Norio Ishitsuka , Nobuyoshi Hattori , Tomio Iwasaki
发明人： Norio Ishitsuka , Nobuyoshi Hattori , Tomio Iwasaki
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/26513 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： After a gate electrode is formed on a main surface of a semiconductor substrate, low concentration layers are formed on the main surface of the semiconductor substrate by implanting impurities therein, with using the gate electrode as a mask. Thereafter, first sidewalls and second sidewalls are formed on the both side surfaces of the gate electrode. Subsequently, nitrogen or the like is ion-implanted into the semiconductor substrate, with using the first sidewalls, the second sidewalls and the gate electrode as a mask, thereby forming a crystallization-control region (CCR) on the main surface of the semiconductor substrate. Then, after the second sidewalls are removed, high concentration layers for a source and a drain are formed on the main surface of the semiconductor substrate.
摘要翻译：在半导体衬底的主表面上形成栅电极之后，通过使用栅电极作为掩模，在半导体衬底的主表面上注入杂质，形成低浓度层。此后，在栅电极的两个侧表面上形成第一侧壁和第二侧壁。随后，使用第一侧壁，第二侧壁和栅电极作为掩模，将氮等离子注入到半导体衬底中，从而在半导体衬底的主表面上形成结晶化控制区域（CCR）。然后，在去除第二侧壁之后，在半导体衬底的主表面上形成用于源极和漏极的高浓度层。

6. 发明授权

US07674668B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07674668B2
公开(公告)日：2010-03-09
申请号：US12005444
申请日：2007-12-26
申请人： Norio Ishitsuka , Nobuyoshi Hattori , Tomio Iwasaki
发明人： Norio Ishitsuka , Nobuyoshi Hattori , Tomio Iwasaki
IPC分类号： H01L21/336 , H01L21/265
CPC分类号： H01L21/26506 , H01L21/26513 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： After a gate electrode is formed on a main surface of a semiconductor substrate, low concentration layers are formed on the main surface of the semiconductor substrate by implanting impurities therein, with using the gate electrode as a mask. Thereafter, first sidewalls and second sidewalls are formed on the both side surfaces of the gate electrode. Subsequently, nitrogen or the like is ion-implanted into the semiconductor substrate, with using the first sidewalls, the second sidewalls and the gate electrode as a mask, thereby forming a crystallization-control region (CCR) on the main surface of the semiconductor substrate. Then, after the second sidewalls are removed, high concentration layers for a source and a drain are formed on the main surface of the semiconductor substrate.
摘要翻译：在半导体衬底的主表面上形成栅电极之后，通过使用栅电极作为掩模，在半导体衬底的主表面上注入杂质，形成低浓度层。此后，在栅电极的两个侧表面上形成第一侧壁和第二侧壁。随后，使用第一侧壁，第二侧壁和栅电极作为掩模，将氮等离子注入到半导体衬底中，从而在半导体衬底的主表面上形成结晶化控制区域（CCR）。然后，在去除第二侧壁之后，在半导体衬底的主表面上形成用于源极和漏极的高浓度层。

7. 发明申请

US20050269662A1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050269662A1
公开(公告)日：2005-12-08
申请号：US11139002
申请日：2005-05-25
申请人： Norio Ishitsuka , Jun Tanaka , Tomio Iwasaki , Hiroyuki Ohta
发明人： Norio Ishitsuka , Jun Tanaka , Tomio Iwasaki , Hiroyuki Ohta
IPC分类号： H01L21/76 , H01L21/312 , H01L21/316 , H01L21/8234 , H01L21/8247 , H01L27/08 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： H01L21/823481 , H01L21/02134 , H01L21/02137 , H01L21/02203 , H01L21/3124 , H01L21/31662 , H01L29/7833
摘要： To suppress occurrence of dislocation in a substrate of a semiconductor device at an end portion of a gate electrode. Provided is a semiconductor device having a plurality of element formation regions formed over the main surface of a semiconductor substrate, an element isolation trench located between the element formation regions and having an element isolation insulating film embedded therein, and a gate insulating film, a gate electrode and a plurality of interconnect layers formed thereabove, each formed in the element formation region, wherein the element isolation trench has a thermal oxide film formed between the semiconductor substrate and the element isolation insulating film, and the element isolation film has a great number of micro-pores formed inside thereof and is more porous than the thermal oxide film.
摘要翻译：为了抑制在栅电极的端部处的半导体器件的衬底中的位错的发生。提供了一种半导体器件，其具有形成在半导体衬底的主表面上的多个元件形成区域，位于元件形成区域之间并且具有嵌入元件隔离绝缘膜的元件隔离沟槽，以及栅极绝缘膜，栅极电极和形成在其上的多个互连层，各自形成在元件形成区域中，其中元件隔离沟槽具有形成在半导体衬底和元件隔离绝缘膜之间的热氧化膜，并且元件隔离膜具有大量在其内形成的微孔比热氧化膜多孔。

8. 发明授权

US07279769B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07279769B2
公开(公告)日：2007-10-09
申请号：US11139002
申请日：2005-05-25
申请人： Norio Ishitsuka , Jun Tanaka , Tomio Iwasaki , Hiroyuki Ohta
发明人： Norio Ishitsuka , Jun Tanaka , Tomio Iwasaki , Hiroyuki Ohta
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L21/823481 , H01L21/02134 , H01L21/02137 , H01L21/02203 , H01L21/3124 , H01L21/31662 , H01L29/7833
摘要： To suppress occurrence of dislocation in a substrate of a semiconductor device at an end portion of a gate electrode. Provided is a semiconductor device having a plurality of element formation regions formed over the main surface of a semiconductor substrate, an element isolation trench located between the element formation regions and having an element isolation insulating film embedded therein, and a gate insulating film, a gate electrode and a plurality of interconnect layers formed thereabove, each formed in the element formation region, wherein the element isolation trench has a thermal oxide film formed between the semiconductor substrate and the element isolation insulating film, and the element isolation film has a great number of micro-pores formed inside thereof and is more porous than the thermal oxide film.
摘要翻译：为了抑制在栅电极的端部处的半导体器件的衬底中的位错的发生。提供了一种半导体器件，其具有形成在半导体衬底的主表面上的多个元件形成区域，位于元件形成区域之间并且具有嵌入元件隔离绝缘膜的元件隔离沟槽，以及栅极绝缘膜，栅极电极和形成在其上的多个互连层，各自形成在元件形成区域中，其中元件隔离沟槽具有形成在半导体衬底和元件隔离绝缘膜之间的热氧化膜，并且元件隔离膜具有大量在其内形成的微孔比热氧化膜多孔。

9. 发明授权

US07701062B2 Semiconductor device and method for producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07701062B2
公开(公告)日：2010-04-20
申请号：US11834081
申请日：2007-08-06
申请人： Tomio Iwasaki , Hideo Miura
发明人： Tomio Iwasaki , Hideo Miura
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/53238 , H01L21/76846 , H01L21/76849 , H01L21/7685 , H01L23/53228 , H01L23/53242 , H01L23/53252 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： Provided, is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film. In the device, the materials for the conductor film and the neighboring film are so selected that the difference between the short side, ap, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the short side, an, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|ap−an|/ap}×100=A (%) and the difference between the long side, bp, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the long side, bn, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|bp−bn|/bp}×100=B (%) satisfy an inequality of {A+B×(ap/bp)}
摘要翻译：提供的是具有分层互连结构的可靠的半导体器件，其可以不产生空隙和互连故障的问题，其中分层互连结构包括导体膜和相邻的膜，如此分层在半导体衬底上，邻近膜被接触与导体膜。在该器件中，用于导体膜和相邻膜的材料被选择成使得构成具有导体膜的最小自由能和短边的平面的矩形单位电池的短边面ap之间的差，，构成具有相邻膜的最小自由能的平面的矩形单元电池，矩形单位电池的长边，bp之间的差异为{| ap-an | / ap}×100 = A（％）构成具有相邻膜的最小自由能的构成平面的矩形单位电池的导体膜和长边bn的最小自由能的平面{| bp-bn | / bp}×100 = B （％）满足{A + B×（ap / bp）} <13的不等式。在此，导体膜的扩散被延迟。

10. 发明申请

US20060183324A1 Semiconductor device and method for producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060183324A1
公开(公告)日：2006-08-17
申请号：US11392540
申请日：2006-03-30
申请人： Tomio Iwasaki , Hideo Miura
发明人： Tomio Iwasaki , Hideo Miura
IPC分类号： H01L21/44
CPC分类号： H01L23/53238 , H01L21/76846 , H01L21/76849 , H01L21/7685 , H01L23/53228 , H01L23/53242 , H01L23/53252 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： Provided is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film. In the device, the materials for the conductor film and the neighboring film are so selected that the difference between the short side, ap, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the short side, an, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|ap−an|/ap}×100=A (%) and the difference between the long side, bp, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the long side, bn, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|bp−bn|/bp}×100=B (%) satisfy an inequality of {A+B×(ap/bp)}
摘要翻译：提供了一种具有层状互连结构的可靠的半导体器件，其可以不产生空隙和互连故障的问题，其中分层互连结构包括导体膜和相邻的膜，如此分层在半导体衬底上，邻近膜与导体膜。在该器件中，用于导体膜和相邻膜的材料被选择成使构成具有最小自由能的平面的矩形单元电池的短边，即< 导体薄膜和构成具有相邻薄膜的最小自由能的平面的矩形单元电池的短边，即_{n x100 = A（％）和构成该矩阵单位单元的长边，b P 之间的差异构成具有相邻膜的最小自由能的平面的矩形单位电池的导体膜和长边的最小自由能的平面{| b＆lt; p＆lt; x100 = B（％）满足{A + Bx（a _{p b＆lt; p＆lt; p＆gt;）} <13。在此，导体膜的扩散被延迟。}}

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式