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61. 发明申请

US20040053516A1 Method for producing silicon wafer and silicon wafer 有权
标题翻译：硅晶片和硅晶片的制造方法
公开(公告)号：US20040053516A1
公开(公告)日：2004-03-18
申请号：US10432861
申请日：2003-05-28
发明人： Yoshinobu Nakada , Hiroyuka Shiraki
IPC分类号： H01L021/31 , H01L021/469 , H01L021/26 , H01L021/324 , H01L021/42 , H01L021/477
CPC分类号： H01L21/3225
摘要： Silicon wafer W is thermal-annealed in atmosphere G to form new vacancies therein in a thermal annealing step and atmosphere G in the thermal annealing step contains a nitride gas having a lower decomposition temperature than a decomposable temperature of N2 so that the thermal annealing is carried out at a lower temperature or for a short time to suppress generation of slip and to provide satisfactory surface roughness.
摘要翻译：将硅晶片W在气氛G中进行热退火，在热退火工序中形成新的空位，热退火工序中的气氛G含有分解温度低于N2的分解温度的氮化物气体，进行热退火在较低温度下或短时间内排出以抑制滑移的产生并提供令人满意的表面粗糙度。

62. 发明申请

US20040053513A1 Method for production of semiconductor components 失效
标题翻译：制造半导体元件的方法
公开(公告)号：US20040053513A1
公开(公告)日：2004-03-18
申请号：US10625118
申请日：2003-07-22
申请人： Osram Opto Semiconductors GMBH & Co. OHG, a Regensburg Bavaria, corporation
发明人： Volker Harle
IPC分类号： H01L021/31
CPC分类号： H01L21/30604
摘要： The present invention relates to a method for the production of semiconductor components. This method comprises the steps applying masking layers and components on epitaxial semiconductor substrates within the epitaxy reactor without removal of the substrate from the reactor. The masking layers may be HF soluble such that a gas etchant may be introduced within the reactor so as to etch a select number and portion of masking layers. This method may be used for production of lateral integrated components on a substrate wherein the components may be of the same or different type. Such types include electronic and optoelectronic components. Numerous masking layers may be applied, each defining particular windows intended to receive each of the various components. In the reactor, the masks may be selectively removed, then the components grown in the newly exposed windows.
摘要翻译：本发明涉及半导体元件的制造方法。该方法包括在外延反应器内的外延半导体衬底上施加掩模层和组件而不从反应器中去除衬底的步骤。掩蔽层可以是HF可溶的，使得可以在反应器内引入气体蚀刻剂，以便蚀刻选择数量和部分掩蔽层。该方法可以用于在衬底上生产横向集成组件，其中组件可以具有相同或不同的类型。这些类型包括电子和光电子元件。可以应用许多掩蔽层，每个屏蔽层限定旨在接收各种部件中的每一个的特定窗口。在反应器中，可以选择性地去除掩模，然后在新露出的窗口中生长组分。

63. 发明申请

US20040051135A1 Method for forming a protective buffer layer for high temperature oxide processing 有权
标题翻译：形成用于高温氧化物处理的保护缓冲层的方法
公开(公告)号：US20040051135A1
公开(公告)日：2004-03-18
申请号：US10423162
申请日：2003-04-24
申请人： Mosel Vitelic, Inc.
发明人： Zhong Dong , Chuck Jang
IPC分类号： H01L029/788 , H01L021/31 , H01L021/469
CPC分类号： H01L29/788 , H01L21/28273 , H01L21/3144 , H01L21/3145 , H01L29/511 , H01L29/66825
摘要： A thin buffer layer of SiON is formed on the top surface of the floating gate, in order to protect the polysilicon surface from attack by atomic chlorine produced during the formation of the high temperature oxide of the ONO stack. The buffer layer can also be formed on other dielectric surfaces which are otherwise subject to adverse conditions in subsequent processing, such as the nitride layer in the ONO dielectric stack.
摘要翻译：在浮栅的顶表面上形成有薄的缓冲层SiON，以便保护多晶硅表面免受在ONO堆叠的高温氧化物形成过程中产生的原子氯的侵蚀。缓冲层也可以形成在其它电介质表面上，否则在后续处理中会受到不利条件的影响，例如ONO电介质叠层中的氮化物层。

64. 发明申请

US20040048960A1 Compositions for preparing low dielectric materials 有权
标题翻译：用于制备低电介质材料的组合物
公开(公告)号：US20040048960A1
公开(公告)日：2004-03-11
申请号：US10638942
申请日：2003-05-20
发明人： Brian Keith Peterson , John Francis Kirner , Scott Jeffrey Weigel , James Edward MacDougall , Lisa Deis , Thomas Albert Braymer , Keith Douglas Campbell , Martin Devenney , C. Eric Ramberg , Konstantinos Chondroudis , Keith Cendak
IPC分类号： H01L021/31 , H01L021/469 , C08K005/24
CPC分类号： H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/3122 , H01L21/31695
摘要： Low dielectric materials and films comprising same have been identified for improved performance when used as performance materials, for example, in interlevel dielectrics integrated circuits as well as methods for making same. In one aspect of the present invention, the performance of the dielectric material may be improved by controlling the weight percentage of ethylene oxide groups in the at least one porogen.
摘要翻译：当用作性能材料时，例如在层间电介质集成电路中使用低电介质材料和包含它们的薄膜以及用于制造它们的方法来改进性能。在本发明的一个方面，可以通过控制至少一种致孔剂中的环氧乙烷基团的重量百分数来提高介电材料的性能。

65. 发明申请

US20040048490A1 Interlayer insulation film used for multilayer interconnect of semiconductor integrated circuit and method of manufacturing the same 有权
标题翻译：用于半导体集成电路的多层互连的层间绝缘膜及其制造方法
公开(公告)号：US20040048490A1
公开(公告)日：2004-03-11
申请号：US10657416
申请日：2003-09-08
申请人： ASM JAPAN K.K.
发明人： Naoto Tsuji , Fumitoshi Ozaki , Satoshi Takahashi
IPC分类号： H01L021/31 , H01L021/469
CPC分类号： H01L21/02126 , C23C16/30 , C23C16/56 , H01L21/022 , H01L21/02216 , H01L21/02274 , H01L21/31633 , H01L21/3212 , H01L21/76832 , H01L21/76835 , H01L21/7684
摘要： An interlayer insulation film for multilayer interconnect of a semiconductor integrated circuit is formed by forming a first insulation film on a substrate by plasma CVD using a silicon-containing hydrocarbon gas; and continuously forming a second insulation film on the first insulation film at a thickness less than the first insulation film in situ by plasma CVD using a silicon-containing hydrocarbon gas and an oxidizing gas. The second insulation film has a hardness of 6 GPa or higher and is used as a polishing stop layer.
摘要翻译：通过使用含硅烃气体通过等离子体CVD法在基板上形成第一绝缘膜来形成半导体集成电路的多层互连用层间绝缘膜，并且通过使用含硅烃气体和氧化气体的等离子体CVD在第一绝缘膜上以小于第一绝缘膜的厚度连续地形成第二绝缘膜。第二绝缘膜的硬度为6GPa以上，用作抛光停止层。

66. 发明申请

US20040043633A1 Systems and methods for forming refractory metal oxide layers 有权
$Systems and methods for forming refractory metal oxide layers$
标题翻译：用于形成难熔金属氧化物层的系统和方法
公开(公告)号：US20040043633A1
公开(公告)日：2004-03-04
申请号：US10229653
申请日：2002-08-28
申请人： MICRON TECHNOLOGY, INC.
发明人： Brian A. Vaartstra
IPC分类号： H01L021/8234 , H01L021/8244 , H01L021/31 , H01L021/469 , C23C016/00
CPC分类号： H01L21/02205 , C23C16/405 , C23C16/45553 , H01L21/02183 , H01L21/02271 , H01L21/0228 , H01L21/31604 , H01L21/31683 , H01L28/40
摘要： A method of forming (and apparatus for forming) refractory metal oxide layers, such as tantalum pentoxide layers, on substrates by using vapor deposition processes with refractory metal precursor compounds and ethers.
摘要翻译：通过使用难熔金属前体化合物和醚的气相沉积工艺在基底上形成（以及用于形成）难熔金属氧化物层（例如五氧化二钽）的方法。

67. 发明申请

US20040043570A1 Semiconductor device and process for producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20040043570A1
公开(公告)日：2004-03-04
申请号：US10649613
申请日：2003-08-28
申请人： Hitachi, Ltd. , Tokyo Institute of Technology
发明人： Yoshihisa Fujisaki , Hiroshi Ishihara
IPC分类号： H01L021/4763 , H01L021/336 , H01L021/3205 , H01L021/469 , H01L021/31
CPC分类号： H01L21/28185 , H01L21/28202 , H01L29/513 , H01L29/518
摘要： With regard to a semiconductor apparatus thermally stable in a post process and suitable for fabricating a gate insulator having a laminated structure with various high permittivity oxides and a process of producing the same, in order to achieve high function formation of a gate insulator 8, a silicon nitride film specific inductive capacity of which is approximately twice as much as that of silicon oxide and which is thermally stable and is not provided with SinullH bond, is used as at least a portion of the gate insulator 8. Further, an effective thickness of a gate insulator forming a multilayered structure insulator laminated with a metal oxide having high dielectric constant, in conversion to silicon oxide, can be thinned to less than 3 nm while restraining leakage current.
摘要翻译：关于在后工序中热稳定并适于制造具有各种高介电常数氧化物的层叠结构的栅极绝缘体的半导体装置及其制造方法，为了实现栅绝缘体8的高功能形成，氮化硅膜的比介电常数大约是氧化硅的两倍，并且是热稳定的并且不具有Si-H键，其被用作栅极绝缘体8的至少一部分。此外，有效的形成与具有高介电常数的金属氧化物层叠的多层结构绝缘体的栅极绝缘体的厚度可以在抑制漏电流的同时变薄至小于3nm。

68. 发明申请

US20040038516A1 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20040038516A1
公开(公告)日：2004-02-26
申请号：US10413944
申请日：2003-04-15
申请人： Samsung Electronics Co., Ltd.
发明人： Ju-Wan Kim , Shin-Hye Kim , Ju-Bum Lee , Hyong-Soo Kim
IPC分类号： H01L021/3205 , H01L021/4763 , H01L021/31 , H01L021/469
CPC分类号： H01L21/02129 , H01L21/02271 , H01L21/02315 , H01L21/02337 , H01L21/31625 , H01L21/76826 , H01L21/76829 , H01L21/76837
摘要： A method of manufacturing a semiconductor device by which a generation of a void is prevented after depositing an interlayer dielectric material. First, a plurality of conductive patterns are formed on a substrate and then, a capping insulation layer is formed on the conductive patterns. The capping insulation layer is treated with plasma, and an interlayer dielectric material is deposited on the plasma treated capping insulation layer. The dependency of the interlayer dielectric on the type of material and form of an underlying layer is reduced to improve a gap-filling characteristic, especially for a gap having a high aspect ratio. An improved gap-filling characteristic is accomplished and the formation of all or substantially all of the voids from forming in a gap is prevented even though an interlayer dielectric is deposited under a conventional deposition conditions.
摘要翻译：一种制造半导体器件的方法，其中在沉积层间电介质材料之后防止产生空隙。首先，在基板上形成多个导电图案，然后在导电图案上形成封盖绝缘层。用等离子体处理封盖绝缘层，并且在等离子体处理的封盖绝缘层上沉积层间电介质材料。层间电介质对材料类型和下层的形式的依赖性被降低以改善间隙填充特性，特别是对于具有高纵横比的间隙。实现了改进的间隙填充特性，并且即使在常规沉积条件下沉积层间电介质，也可防止在间隙中形成全部或基本上所有空隙的形成。

69. 发明申请

US20040038486A1 Plasma method and apparatus for processing a substrate 有权
公开(公告)号：US20040038486A1
公开(公告)日：2004-02-26
申请号：US10461083
申请日：2003-06-12
申请人： APPLIED MATERIALS, INC.
发明人： Thai Cheng Chua , Philip Allan Kraus , John Holland
IPC分类号： H01L021/31 , H01L021/336 , H01L021/3205 , H01L021/469 , H01L021/4763
CPC分类号： H01L21/28202 , H01J37/321 , H01L21/3144 , H01L21/3185
摘要： Embodiments of the invention generally provide a method of forming a nitride gate dielectric layer. The method includes generating a nitrogen-containing plasma in a processing chamber via introduction of a nitrogen-containing processing gas into the processing chamber and the application of an ionizing energy to the processing gas, and pulsing the ionizing energy to maintain a mean temperature of electrons in the nitrogen-containing plasma of less than about 0.7 eV.

70. 发明申请

US20040033700A1 Electronic device manufacture 失效
标题翻译：电子设备制造
公开(公告)号：US20040033700A1
公开(公告)日：2004-02-19
申请号：US10453337
申请日：2003-06-03
申请人： Shipley Company, L.L.C.
发明人： Dana A. Gronbeck , Michael K. Gallagher , Jeffrey M. Calvert , Gregory P. Prokopowicz , Timothy G. Adams
IPC分类号： H01L021/469 , H01L021/4763 , H01L021/31
CPC分类号： H01L21/02126 , C09D183/04 , C09D183/14 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/31695 , Y10T428/249987
摘要： Methods for depositing uniform, pinhole-defect free organic polysilica coatings are provided. These methods allow for the use of these materials as spin-on cap layers in the manufacture of integrated circuits.
摘要翻译：提供了沉积均匀的针孔缺陷有机聚硅氧烷涂层的方法。这些方法允许在制造集成电路中使用这些材料作为旋涂帽层。

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