基本信息:
- 专利标题： Semiconductor device and process for producing the same
- 专利标题（中）：半导体装置及其制造方法
- 申请号：US10649613 申请日：2003-08-28
- 公开(公告)号：US20040043570A1 公开(公告)日：2004-03-04
- 发明人： Yoshihisa Fujisaki , Hiroshi Ishihara
- 申请人： Hitachi, Ltd. , Tokyo Institute of Technology
- 申请人地址： null null
- 专利权人： Hitachi, Ltd.,Tokyo Institute of Technology
- 当前专利权人： Hitachi, Ltd.,Tokyo Institute of Technology
- 当前专利权人地址： null null
- 优先权： JP2001-129243 20010426
- 主分类号： H01L021/4763
- IPC分类号： H01L021/4763 ; H01L021/336 ; H01L021/3205 ; H01L021/469 ; H01L021/31
摘要：
With regard to a semiconductor apparatus thermally stable in a post process and suitable for fabricating a gate insulator having a laminated structure with various high permittivity oxides and a process of producing the same, in order to achieve high function formation of a gate insulator 8, a silicon nitride film specific inductive capacity of which is approximately twice as much as that of silicon oxide and which is thermally stable and is not provided with SinullH bond, is used as at least a portion of the gate insulator 8. Further, an effective thickness of a gate insulator forming a multilayered structure insulator laminated with a metal oxide having high dielectric constant, in conversion to silicon oxide, can be thinned to less than 3 nm while restraining leakage current.
摘要（中）：
关于在后工序中热稳定并适于制造具有各种高介电常数氧化物的层叠结构的栅极绝缘体的半导体装置及其制造方法，为了实现栅绝缘体8的高功能形成， 氮化硅膜的比介电常数大约是氧化硅的两倍，并且是热稳定的并且不具有Si-H键，其被用作栅极绝缘体8的至少一部分。此外，有效的 形成与具有高介电常数的金属氧化物层叠的多层结构绝缘体的栅极绝缘体的厚度可以在抑制漏电流的同时变薄至小于3nm。
公开/授权文献:
- US07033958B2 Semiconductor device and process for producing the same 公开/授权日：2006-04-25