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1. 发明申请

US20040038516A1 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20040038516A1
公开(公告)日：2004-02-26
申请号：US10413944
申请日：2003-04-15
申请人： Samsung Electronics Co., Ltd.
发明人： Ju-Wan Kim , Shin-Hye Kim , Ju-Bum Lee , Hyong-Soo Kim
IPC分类号： H01L021/3205 , H01L021/4763 , H01L021/31 , H01L021/469
CPC分类号： H01L21/02129 , H01L21/02271 , H01L21/02315 , H01L21/02337 , H01L21/31625 , H01L21/76826 , H01L21/76829 , H01L21/76837
摘要： A method of manufacturing a semiconductor device by which a generation of a void is prevented after depositing an interlayer dielectric material. First, a plurality of conductive patterns are formed on a substrate and then, a capping insulation layer is formed on the conductive patterns. The capping insulation layer is treated with plasma, and an interlayer dielectric material is deposited on the plasma treated capping insulation layer. The dependency of the interlayer dielectric on the type of material and form of an underlying layer is reduced to improve a gap-filling characteristic, especially for a gap having a high aspect ratio. An improved gap-filling characteristic is accomplished and the formation of all or substantially all of the voids from forming in a gap is prevented even though an interlayer dielectric is deposited under a conventional deposition conditions.
摘要翻译：一种制造半导体器件的方法，其中在沉积层间电介质材料之后防止产生空隙。首先，在基板上形成多个导电图案，然后在导电图案上形成封盖绝缘层。用等离子体处理封盖绝缘层，并且在等离子体处理的封盖绝缘层上沉积层间电介质材料。层间电介质对材料类型和下层的形式的依赖性被降低以改善间隙填充特性，特别是对于具有高纵横比的间隙。实现了改进的间隙填充特性，并且即使在常规沉积条件下沉积层间电介质，也可防止在间隙中形成全部或基本上所有空隙的形成。

2. 发明申请

US20020135072A1 Semiconductor memory device for reducing parasitic bit line capacitance and method of fabricating the same 有权
标题翻译：用于减少寄生位线电容的半导体存储器件及其制造方法
公开(公告)号：US20020135072A1
公开(公告)日：2002-09-26
申请号：US10102312
申请日：2002-03-19
申请人： Samsung Electronics Co., Ltd.
发明人： Myoung-Hee Han , Young-Hoon Park , Ju-Wan Kim , Ju-Bum Lee
IPC分类号： H01L023/48
CPC分类号： H01L27/10855 , H01L21/76897 , H01L23/5222 , H01L27/10885 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device for reducing parasitic bit line capacitance and a method of fabricating the same are provided. The semiconductor memory device includes a conductive pad formed on a semiconductor substrate and a first interlayer insulating layer having a first contact hole that exposes the conductive pad. The first interlayer insulating layer is formed on the conductive pad and the semiconductor substrate. Bit line stacks are formed on the first interlayer insulating layer. Bit line spacers are formed from a combination of materials having different dielectric constants on the sidewalls of the bit line stack to reduce the parasitic bit line capacitance. Preferably, the bit line spacers are stack layers including silicon nitride, silicon oxide, and silicon nitride. A second interlayer insulating layer having a second contact hole is formed on the bit line stack. A conductive plug fills the first and second contact holes. A storage electrode of a capacitor is formed on the conductive plug to be connected to the conductive pad.
摘要翻译：提供了用于减小寄生位线电容的半导体存储器件及其制造方法。半导体存储器件包括形成在半导体衬底上的导电焊盘和具有暴露导电焊盘的第一接触孔的第一层间绝缘层。第一层间绝缘层形成在导电焊盘和半导体衬底上。位线堆叠形成在第一层间绝缘层上。位线间隔物由位线叠层的侧壁上具有不同介电常数的材料的组合形成，以减少寄生位线电容。优选地，位线间隔物是包括氮化硅，氧化硅和氮化硅的堆叠层。在位线叠层上形成具有第二接触孔的第二层间绝缘层。导电塞填充第一和第二接触孔。电容器的存储电极形成在导电插头上，以连接到导电焊盘。

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