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61. 发明授权

US07444637B2 Systems and methods for scheduling coprocessor resources in a computing system 有权
标题翻译：在计算系统中调度协处理器资源的系统和方法
公开(公告)号：US07444637B2
公开(公告)日：2008-10-28
申请号：US10777797
申请日：2004-02-12
申请人： Steve Pronovost , Anuj B. Gosalia , Bryan L. Langley , Hideyuki Nagase
发明人： Steve Pronovost , Anuj B. Gosalia , Bryan L. Langley , Hideyuki Nagase
IPC分类号： G06F9/46 , G06F13/28 , G06F9/34 , G06F15/76
CPC分类号： G06F13/30 , G06F9/4881 , G06F9/5016
摘要： Systems and methods for scheduling coprocessing resources in a computing system are provided without redesigning the coprocessor. In various embodiments, a system of preemptive multitasking is provided achieving benefits over cooperative multitasking by any one or more of (1) executing rendering commands sent to the coprocessor in a different order than they were submitted by applications; (2) preempting the coprocessor during scheduling of non-interruptible hardware; (3) allowing user mode drivers to build work items using command buffers in a way that does not compromise security; (4) preparing DMA buffers for execution while the coprocessor is busy executing a previously prepared DMA buffer; (5) resuming interrupted DMA buffers; and (6) reducing the amount of memory needed to run translated DMA buffers.
摘要翻译：提供了一种用于在计算系统中调度协处理资源的系统和方法，而不重新设计协处理器。在各种实施例中，提供了一种抢占式多任务的系统，其通过以下方式中的任何一个或多个实现协作多任务的优点：（1）以与应用提交的顺序不同的顺序执行发送到协处理器的呈现命令; （2）在调度不可中断硬件期间抢占协处理器; （3）允许用户模式驱动程序以不损害安全性的方式使用命令缓冲区构建工作项; （4）在协处理器忙于执行预先准备的DMA缓冲器时，准备执行DMA缓冲器; （5）恢复中断DMA缓冲区; 和（6）减少运行转换的DMA缓冲区所需的内存量。

62. 发明申请

US20070162658A1 Data transfer apparatus, storage device control apparatus and control method using storage device control apparatus 审中-公开
标题翻译：数据传送装置，存储装置控制装置及使用存储装置控制装置的控制方法
公开(公告)号：US20070162658A1
公开(公告)日：2007-07-12
申请号：US11649108
申请日：2007-01-04
申请人： Masayuki Furukawa , Takahiko Takeda
发明人： Masayuki Furukawa , Takahiko Takeda
IPC分类号： G06F5/00
CPC分类号： G06F3/061 , G06F3/0601 , G06F3/0656 , G06F3/0659 , G06F3/067 , G06F13/1642 , G06F13/28 , G06F13/30 , G06F2003/0692
摘要： A data transfer apparatus includes a memory having first and second queues for storing data transfer information that includes information specifying a first memory area and information specifying a second memory area, a first processor which registers the data transfer information in the first or second queue, and a second processor performing a processing to transfer data stored in the first memory area to the second memory area. The second processor reads out the data transfer information registered in the first queue, transfers the data based on the read data transfer information, and decides if data transfer information succeeding to the read data transfer information is registered in the first queue. If the succeeding data transfer information is registered, the second processor reads out the succeeding data transfer information from the first queue, and performs the data transfer processing based on the read data transfer information.
摘要翻译：数据传送装置包括具有第一和第二队列的存储器，用于存储包括指定第一存储区域的信息和指定第二存储区域的信息的数据传输信息，将数据传送信息登记在第一或第二队列中的第一处理器，以及执行将存储在第一存储区域中的数据传送到第二存储区域的处理的第二处理器。第二处理器读出登记在第一队列中的数据传送信息，基于读取的数据传送信息传送数据，并且判定在读取的数据传送信息之后的数据传送信息是否被登记在第一队列中。如果后续数据传送信息被登记，则第二处理器从第一队列读出后续数据传送信息，并且基于读取的数据传送信息执行数据传送处理。

63. 发明授权

US07051123B1 Data transfer engine of a processor having a plurality of modules 有权
标题翻译：具有多个模块的处理器的数据传输引擎
公开(公告)号：US07051123B1
公开(公告)日：2006-05-23
申请号：US09710192
申请日：2000-11-10
申请人： David Baker , Christopher Basoglu , Benjamin Cutler , Gregorio Gervasio , Woobin Lee , Yatin Mundkur , Toru Nojiri , John O'Donnell , Ashok Raman , Eric Rehm , Radhika Thekkath
发明人： David Baker , Christopher Basoglu , Benjamin Cutler , Gregorio Gervasio , Woobin Lee , Yatin Mundkur , Toru Nojiri , John O'Donnell , Ashok Raman , Eric Rehm , Radhika Thekkath
IPC分类号： G06F3/00
CPC分类号： G06F13/30 , G06F13/1605
摘要： In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus.An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.
摘要翻译：在具有处理器，主存储器和多个I / O设备的多个模块的信息处理系统中，用于在处理器，主存储器和I / O设备之间执行数据传送操作的数据传送开关包括请求总线其具有用于从多个模块中的每一个接收读取和写入请求的请求总线仲裁器。处理器存储器总线被配置为从包括处理器的预定数量的模块接收地址和数据信息。处理器存储器总线具有用于从耦合到处理器存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。内部存储器总线被配置为从包括存储器和I / O设备的预定数量的模块接收地址和数据信息。内部存储器总线具有用于从耦合到内部存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。收发器系统耦合到处理器存储器总线和内部存储器总线，用于在处理器存储器总线和内部存储器总线之间传送数据。

64. 发明申请

US20060015651A1 Apparatus and method for supporting memory management in an offload of network protocol processing 有权
标题翻译：用于在卸载网络协议处理中支持存储器管理的装置和方法
公开(公告)号：US20060015651A1
公开(公告)日：2006-01-19
申请号：US10890978
申请日：2004-07-14
申请人： Douglas Freimuth , Elbert Hu , Ronald Mraz , Erich Nahum , Prashant Pradhan , Sambit Sahu , John Tracey
发明人： Douglas Freimuth , Elbert Hu , Ronald Mraz , Erich Nahum , Prashant Pradhan , Sambit Sahu , John Tracey
IPC分类号： G06F15/16
CPC分类号： G06F13/30
摘要： A number of improvements in network adapters that offload protocol processing from the host processor are provided. Specifically, mechanisms for handling memory management and optimization within a system utilizing an offload network adapter are provided. The memory management mechanism permits both buffered sending and receiving of data as well as zero-copy sending and receiving of data. In addition, the memory management mechanism permits grouping of DMA buffers that can be shared among specified connections based on any number of attributes. The memory management mechanism further permits partial send and receive buffer operation, delaying of DMA requests so that they may be communicated to the host system in bulk, and expedited transfer of data to the host system.
摘要翻译：提供了从主机处理器卸载协议处理的网络适配器的许多改进。具体地说，提供了利用卸载网络适配器在系统内处理存储器管理和优化的机制。存储器管理机制允许数据的缓冲发送和接收以及零拷贝发送和接收数据。此外，存储器管理机制允许基于任何数量的属性对可以在指定连接之间共享的DMA缓冲器进行分组。存储器管理机制进一步允许部分发送和接收缓冲器操作，延迟DMA请求，使得它们可以批量地传送到主机系统，并且将数据快速传送到主机系统。

65. 发明申请

US20040093439A1 Data processing control apparatus and DMA controller 审中-公开
标题翻译：数据处理控制装置和DMA控制器
公开(公告)号：US20040093439A1
公开(公告)日：2004-05-13
申请号：US10668359
申请日：2003-09-24
申请人： ROHM CO., LTD
发明人： Hiroshi Miura , Hirofumi Inada
IPC分类号： G06F013/28
CPC分类号： G06F13/30
摘要： A DMA controller has a setting register, an operation register, and a setting execution register for storing transfer conditions under which to transfer, by DMA transfer, the transfer conditions for DMA transfer from an external memory to the setting register. The DMA controller also has a multiplexer for alternatively selecting one of the setting register and the setting execution register. The DMA controller further has a controller for performing control so that the selected register is switched alternately between the setting register and the setting execution register every time DMA transfer ends, and a controller for performing control so that, when DMA transfer is started, the data stored in the register selected by the multiplexer is written to the operation register. The DMA controller performs control so that DMA transfer is executed based on the data stored in the operation register.
摘要翻译： DMA控制器具有设置寄存器，操作寄存器和设置执行寄存器，用于存储通过DMA传输将DMA传输的传送条件从外部存储器传送到设置寄存器的传送条件。 DMA控制器还具有用于交替地选择设置寄存器和设置执行寄存器之一的多路复用器。 DMA控制器还具有用于执行控制的控制器，使得每次DMA传送结束时，在设置寄存器和设置执行寄存器之间交替地切换所选择的寄存器，以及用于执行控制的控制器，使得当DMA传输开始时，数据存储在由多路复用器选择的寄存器中的数据被写入操作寄存器。 DMA控制器执行控制，使得基于存储在操作寄存器中的数据执行DMA传输。

66. 发明申请

US20040028053A1 Direct memory access circuit with ATM support 审中-公开
标题翻译：具有ATM支持的直接存储器存取电路
公开(公告)号：US20040028053A1
公开(公告)日：2004-02-12
申请号：US10454750
申请日：2003-06-03
申请人： Catena Networks, Inc.
发明人： Ian Mes
IPC分类号： G06F013/28 , H04L012/56
CPC分类号： H04L12/5601 , G06F13/30 , H04L2012/5652
摘要： A direct memory access (DMA) circuit reduces the number of processor cycles involved in transmitting and receiving asynchronous transfer mode (ATM) cells. The circuit includes a read sequencer, a write sequencer, an ATM control block, a processor interface block, and a DMA arbitration and control block. The DMA arbitration and control block arbitrates between data transmissions on various subchannels. The ATM control block provides ATM functionality to the DMA circuit. The circuit may also respond to a trigger signal and may generate an interrupt signal. In this manner, the processing involved for DMA of ATM cells is improved.
摘要翻译：直接存储器访问（DMA）电路减少了发送和接收异步传输模式（ATM）单元中涉及的处理器周期数。该电路包括读序列器，写定序器，ATM控制块，处理器接口块和DMA仲裁和控制块。 DMA仲裁和控制块在各个子信道上的数据传输之间进行仲裁。 ATM控制块向DMA电路提供ATM功能。电路还可以响应触发信号并且可以产生中断信号。以这种方式，提高了对ATM信元的DMA的处理。

67. 发明申请

US20030033422A1 System and method for interleaving frames with different priorities 有权
标题翻译：用于交织具有不同优先级的帧的系统和方法
公开(公告)号：US20030033422A1
公开(公告)日：2003-02-13
申请号：US09925978
申请日：2001-08-09
发明人： Jeffrey Scott Kuskin , Tao-Fei Samuel Ng , Andrew M. Davidson
IPC分类号： G06F015/16
CPC分类号： H04L47/6215 , G06F13/30 , H04L47/50 , H04L47/564 , H04L49/90 , H04L49/901 , H04L49/9047
摘要： A method of queue management includes: adding entries having a first priority to a first software queue; adding entries having a second priority to a second software queue; reading entries from the first software queue to a physical queue; at a threshold time, flushing entries from the physical queue; after the act of flushing the physical queue, reading entries from the second software queue to the physical queue until a termination criterion is satisfied; after the termination criterion is satisfied, reading entries from the first software queue to the physical queue; and transmitting entries from the physical queue to a network.
摘要翻译：队列管理的方法包括：将具有第一优先级的条目添加到第一软件队列; 将具有第二优先级的条目添加到第二软件队列; 从第一个软件队列读取条目到一个物理队列; 在阈值时间，从物理队列刷新条目; 在刷新物理队列的动作之后，从第二个软件队列读取条目到物理队列，直到满足终止标准; 在满足终止标准之后，从第一个软件队列读取条目到物理队列; 并将条目从物理队列发送到网络。

68. 发明授权

US5884095A Direct memory access controller having programmable timing 失效
标题翻译：具有可编程时序的直接存储器存取控制器
公开(公告)号：US5884095A
公开(公告)日：1999-03-16
申请号：US815731
申请日：1997-03-12
申请人： Jeff W. Wolford , Robert Allan Lester
发明人： Jeff W. Wolford , Robert Allan Lester
IPC分类号： G06F13/28 , G06F13/30 , G06F13/362
CPC分类号： G06F13/30 , G06F13/28 , G06F13/287 , G06F13/3625
摘要： An improved DMA controller having programmable data transfer timings. Not only is the total cycle time programmable, but the active and inactive period of the cycle are also programmable. An active timing register and an inactive timing register are used in conjunction with a countdown timer to determine the active and inactive periods of the data transfer cycle. The active time period is loaded into the timer during the active phase, with the end of the active phase being indicated by the timer timing out. Next, the inactive time period is loaded into the timer, which similarly times out to indicate the end of the inactive phase of the data transfer cycle.
摘要翻译：改进的DMA控制器，具有可编程数据传输定时。总循环时间不仅可编程，而且循环的有效和无效周期也可编程。一个有效的定时寄存器和一个无效的定时寄存器与倒计时定时器结合使用，以确定数据传输周期的有效和无效周期。有效时间段在有效阶段加载到定时器中，活动阶段的结束由定时器超时指示。接下来，将非活动时间段加载到定时器中，其类似地超时以指示数据传送周期的非活动阶段的结束。

69. 发明授权

US5467454A Bus use request adjusting apparatus allowing changing priority levels 失效
标题翻译：总线使用请求调整装置允许改变优先级
公开(公告)号：US5467454A
公开(公告)日：1995-11-14
申请号：US125903
申请日：1993-09-24
申请人： Fumiki Sato
发明人： Fumiki Sato
IPC分类号： G06F13/362 , G06F13/30 , G06F13/364 , G06F13/36 , G06F9/46
CPC分类号： G06F13/364 , G06F13/30
摘要： The bus use efficiency is improved by using a priority level determiner for determining a priority level of a processor to be connected and determining whether to compare the priority level of the processor with that of other processor until a signal indicating the end of a series of processings of the processor becomes valid after a bus use request signal of the processor becomes valid or to compare the priority level of the processor with that of other processor only while the bus use request signal is valid.
摘要翻译：通过使用优先级确定器来确定要连接的处理器的优先级，并且确定是否将处理器的优先级别与其他处理器的优先级进行比较，直到指示一系列处理结束的信号，来提高总线使用效率在处理器的总线使用请求信号变为有效之后，处理器的有效位置变得有效，或者仅在总线使用请求信号有效时将处理器的优先级与其他处理器的优先级进行比较。

70. 发明授权

US5450551A System direct memory access (DMA) support logic for PCI based computer system 失效
标题翻译：用于基于PCI的计算机系统的系统直接存储器访问（DMA）支持逻辑
公开(公告)号：US5450551A
公开(公告)日：1995-09-12
申请号：US68477
申请日：1993-05-28
申请人： Nader Amini , Patrick M. Bland , Bechara F. Boury , Richard G. Hofmann , Terence J. Lohman
发明人： Nader Amini , Patrick M. Bland , Bechara F. Boury , Richard G. Hofmann , Terence J. Lohman
IPC分类号： G06F13/28 , G06F13/30 , G06F13/36 , G06F13/40 , G06F13/364
CPC分类号： G06F13/4018 , G06F13/30 , G06F13/36
摘要： A direct memory access (DMA) support mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU) connected to system memory by a first system bus, and a second system bus connected to the CPU; (ii) a host bridge connecting the second system bus to a peripheral bus; (iii) an input/output (I/O) bridge connecting the peripheral bus to a standard I/O bus, the standard I/O bus having a plurality of standard I/O devices attached thereto; and (v) arbitration logic which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.
摘要翻译：提供直接存储器访问（DMA）支持机制用于计算机系统，其包括（i）通过第一系统总线连接到系统存储器的中央处理单元（CPU）和连接到CPU的第二系统总线; （ii）将第二系统总线连接到外围总线的主桥; （iii）将外围总线连接到标准I / O总线的输入/输出（I / O）桥，标准I / O总线具有连接到其上的多个标准I / O设备; 以及（v）以仲裁模式起作用的仲裁逻辑，用于在竞争访问标准I / O总线的多个标准I / O设备之间进行仲裁，并且在授权模式中，授权选择的标准I / O设备被授权访问到标准I / O总线。 DMA支持机制包括代表所选标准I / O设备执行DMA周期的直接存储器访问（DMA）控制器，以及直接存储器访问（DMA）支持逻辑，用于通过外设总线执行DMA周期。 DMA支持逻辑包括直接连接DMA控制器与I / O桥的边带信号，边带信号包括识别DMA控制器正在执行DMA周期的所选I / O设备的总线大小的信息。

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