专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08990543B2 System and method for generating and using predicates within a single instruction packet 有权
标题翻译：用于在单个指令包内生成和使用谓词的系统和方法
公开(公告)号：US08990543B2
公开(公告)日：2015-03-24
申请号：US12045825
申请日：2008-03-11
申请人： Lucian Codrescu , Robert Allan Lester , Charles Joseph Tabony , Erich James Plondke , Mao Zeng , Suresh Venkumahanti , Ajay Anant Ingle
发明人： Lucian Codrescu , Robert Allan Lester , Charles Joseph Tabony , Erich James Plondke , Mao Zeng , Suresh Venkumahanti , Ajay Anant Ingle
IPC分类号： G06F15/80 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3853 , G06F9/30036 , G06F9/30069 , G06F9/3826 , G06F9/3828 , G06F9/3889
摘要： In a particular embodiment, a method is disclosed that includes receiving an instruction packet including a first instruction and a second instruction that is dependent on the first instruction at a processor having a plurality of parallel execution pipelines, including a first execution pipeline and a second execution pipeline. The method further includes executing in parallel at least a portion of the first instruction and at least a portion of the second instruction. The method also includes selectively committing a second result of executing the at least a portion of the second instruction with the second execution pipeline based on a first result related to execution of the first instruction with the first execution pipeline.
摘要翻译：在特定实施例中，公开了一种方法，其包括在具有多个并行执行流水线的处理器处接收包括依赖于第一指令的第一指令和第二指令的指令分组，所述处理器包括第一执行流水线和第二执行管道。该方法还包括并行地执行第一指令的至少一部分和第二指令的至少一部分。该方法还包括基于与第一执行流水线执行第一指令相关的第一结果，选择性地提交执行具有第二执行流水线的第二指令的至少一部分的第二结果。

2. 发明申请

US20090235051A1 System and Method of Selectively Committing a Result of an Executed Instruction 有权
标题翻译：选择性地执行执行指令的结果的系统和方法
公开(公告)号：US20090235051A1
公开(公告)日：2009-09-17
申请号：US12045825
申请日：2008-03-11
申请人： Lucian Codrescu , Robert Allan Lester , Charles Joseph Tabony , Erich James Plondke , Mao Zeng , Suresh Venkumahanti , Ajay Anant Ingle
发明人： Lucian Codrescu , Robert Allan Lester , Charles Joseph Tabony , Erich James Plondke , Mao Zeng , Suresh Venkumahanti , Ajay Anant Ingle
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/3853 , G06F9/30036 , G06F9/30069 , G06F9/3826 , G06F9/3828 , G06F9/3889
摘要： In a particular embodiment, a method is disclosed that includes receiving an instruction packet including a first instruction and a second instruction that is dependent on the first instruction at a processor having a plurality of parallel execution pipelines, including a first execution pipeline and a second execution pipeline. The method further includes executing in parallel at least a portion of the first instruction and at least a portion of the second instruction. The method also includes selectively committing a second result of executing the at least a portion of the second instruction with the second execution pipeline based on a first result related to execution of the first instruction with the first execution pipeline.
摘要翻译：在特定实施例中，公开了一种方法，其包括在具有多个并行执行流水线的处理器处接收包括依赖于第一指令的第一指令和第二指令的指令分组，所述处理器包括第一执行流水线和第二执行管道。该方法还包括并行地执行第一指令的至少一部分和第二指令的至少一部分。该方法还包括基于与第一执行流水线执行第一指令相关的第一结果，选择性地提交执行具有第二执行流水线的第二指令的至少一部分的第二结果。

3. 发明授权

US06608564B2 Removable memory cartridge system for use with a server or other processor-based device 有权
公开(公告)号：US06608564B2
公开(公告)日：2003-08-19
申请号：US09770100
申请日：2001-01-25
申请人： Christian H. Post , George D. Megason , Brett D. Roscoe , Paul Santeler , John M. MacLaren , John E. Larson , Jeffery Galloway , Siamak Tavallaei , Tim W. Majni , Robert Allan Lester , Anisha Anand , Eric Rose
发明人： Christian H. Post , George D. Megason , Brett D. Roscoe , Paul Santeler , John M. MacLaren , John E. Larson , Jeffery Galloway , Siamak Tavallaei , Tim W. Majni , Robert Allan Lester , Anisha Anand , Eric Rose
IPC分类号： G08B2300
CPC分类号： G06F13/4081 , G06F13/409
摘要： A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.

4. 发明授权

US6078338A Accelerated graphics port programmable memory access arbiter 失效
标题翻译：加速图形端口可编程存储器访问仲裁器
公开(公告)号：US6078338A
公开(公告)日：2000-06-20
申请号：US38412
申请日：1998-03-11
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Gary J. Piccirillo
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Gary J. Piccirillo
IPC分类号： G06F3/14 , G06F13/16 , G09G1/16 , G09G5/00 , G09G5/36
CPC分类号： G06F13/1605 , G06F3/14 , G09G3/003 , G09G5/001 , G09G5/363
摘要： A computer system having a core logic chipset that interconnects a processor(s), a system memory and peripheral device agents. The core logic chipset has a programmable memory access arbiter that may be programmed to optimize accesses by the computer system processor(s) and agents to the system memory for best computer system performance. The memory access arbiter may be programmed specifically for each system agent. An access count register may be incorporated into the core logic chipset wherein each system agent may be represented by a portion of the access count register. The values programmed into the portions of the access count register determine how many memory accesses the associated agent may take before another agent is granted a memory access, and how many cachelines may be transferred during a memory access.
摘要翻译：具有将处理器，系统存储器和外围设备代理器互连的核心逻辑芯片组的计算机系统。核心逻辑芯片组具有可编程存储器访问仲裁器，其可以被编程为优化计算机系统处理器和代理到系统存储器的访问以获得最佳计算机系统性能。存储器访问仲裁器可以针对每个系统代理进行编程。访问计数寄存器可以并入到核心逻辑芯片组中，其中每个系统代理可以由访问计数寄存器的一部分来表示。编程到访问计数寄存器的部分中的值确定在授予存储器访问的另一个代理程序之前，相关联的代理可以执行多少内存访问，以及在存储器访问期间可以传送多少个高速缓存行。

5. 发明授权

US5999743A System and method for dynamically allocating accelerated graphics port memory space 失效
标题翻译：用于动态分配加速图形端口存储空间的系统和方法
公开(公告)号：US5999743A
公开(公告)日：1999-12-07
申请号：US926422
申请日：1997-09-09
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliot
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliot
IPC分类号： G06F3/14 , G09G5/36 , G09G5/39 , B06F13/00
CPC分类号： G06F3/14 , G09G5/363 , G09G2360/121
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. Contiguous virtual memory address space must be allocated for the AGP device within the addressable memory space of the computer system, typically 4 gigabytes using 32 bit addressing. The required amount of virtual memory address space for AGP is determined from the AGP device and the information is put into a register of the core logic so that the computer system software may allocate the required amount of memory and assign a base address thereto during computer system startup or POST.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。必须为计算机系统的可寻址存储空间内的AGP设备分配连续的虚拟内存地址空间，通常使用32位寻址4 GB。从AGP设备确定AGP所需的虚拟内存地址空间量，并将信息放入核心逻辑的寄存器，以便计算机系统软件可以在计算机系统中分配所需量的存储器并分配基地址启动或POST。

6. 发明授权

US5999198A Graphics address remapping table entry feature flags for customizing the operation of memory pages associated with an accelerated graphics port device 失效
标题翻译：图形地址重映射表条目功能标志，用于自定义与加速图形端口设备关联的内存页面的操作
公开(公告)号：US5999198A
公开(公告)日：1999-12-07
申请号：US925772
申请日：1997-09-09
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
IPC分类号： G06F3/14 , G06F12/08 , G09G5/393 , G06F15/16
CPC分类号： G06F3/14 , G06F12/0875 , G09G5/393 , G09G2360/121
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a memory page, and feature flags that may be used to customize the associated memory page.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向存储器页面的基址的地址指针，以及可用于定制关联的存储器页面的特征标志。

7. 发明授权

US5905509A Accelerated Graphics Port two level Gart cache having distributed first level caches 失效
标题翻译：加速图形端口具有分布式一级高速缓存的两级Gart缓存
公开(公告)号：US5905509A
公开(公告)日：1999-05-18
申请号：US941860
申请日：1997-09-30
申请人： Phillip M. Jones , Robert Allan Lester , Kenneth Tom Chin
发明人： Phillip M. Jones , Robert Allan Lester , Kenneth Tom Chin
IPC分类号： G06F12/10 , G06F13/14 , G06F12/08
CPC分类号： G06F12/1027 , G06F12/1081 , G06F2212/681
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page. The core logic chipset caches a subset of the most recently used GART table entries to increase AGP performance when performing the address translation. The core logic chipset uses a two-level GART cache comprising a plurality of first-level GART caches and a common second level GART cache. Each of the plurality of first-level GART caches are coupled to a respective interface in the computer system and effectively de-couple the different interface GART address translations so that GART cache thrashing and cache arbitration delays are substantially reduced. Separate decoupled first-level GART caches for each interface allow concurrent GART address translations among the different interfaces. Individual first-level GART caches may be fined tuned for each associated interface.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向存储器中的图形数据页面的基地址的地址指针，以及可用于定制关联页面的特征标记。核心逻辑芯片组缓存最近使用的GART表项的子集，以在执行地址转换时增加AGP性能。核心逻辑芯片组使用包括多个第一级GART高速缓存和公共第二级GART高速缓存的双级GART缓存。多个第一级GART高速缓存中的每一个耦合到计算机系统中的相应接口，并且有效地解耦不同的接口GART地址转换，使得GART高速缓存颠簸和高速缓存仲裁延迟显着降低。对于每个接口，单独的解耦第一级GART缓存允许在不同接口之间进行并发GART地址转换。单个第一级GART缓存可能会针对每个相关联的接口进行调整。

8. 发明授权

US5692216A Direct memory access controller having programmable timing 失效
标题翻译：具有可编程时序的直接存储器存取控制
公开(公告)号：US5692216A
公开(公告)日：1997-11-25
申请号：US699548
申请日：1996-08-19
申请人： Jeff W. Wolford , Robert Allan Lester
发明人： Jeff W. Wolford , Robert Allan Lester
IPC分类号： G06F13/28 , G06F13/30 , G06F13/362 , G06F13/00
CPC分类号： G06F13/30 , G06F13/28 , G06F13/287 , G06F13/3625
摘要： An improved DMA controller having programmable data transfer timings. Not only is the total cycle time programmable, but the active and inactive period of the cycle are also programmable. An active timing register and an inactive timing register are used in conjunction with a countdown timer to determine the active and inactive periods of the data transfer cycle. The active time period is loaded into the timer during the active phase, with the end of the active phase being indicated by the timer timing out. Next, the inactive time period is loaded into the timer, which similarly times out to indicate the end of the inactive phase of the data transfer cycle.
摘要翻译：改进的DMA控制器，具有可编程数据传输定时。总循环时间不仅可编程，而且循环的有效和无效周期也可编程。一个有效的定时寄存器和一个无效的定时寄存器与倒计时定时器结合使用，以确定数据传输周期的有效和无效周期。有效时间段在有效阶段加载到定时器中，活动阶段的结束由定时器超时指示。接下来，将非活动时间段加载到定时器中，其类似地超时以指示数据传送周期的非活动阶段的结束。

9. 发明授权

US07116241B2 Removable memory cartridge system for use with a server or other processor-based device 有权
公开(公告)号：US07116241B2
公开(公告)日：2006-10-03
申请号：US10437571
申请日：2003-05-14
申请人： Christian H. Post , George D. Megason , Brett D. Roscoe , Paul Santeler , John M. MacLaren , John E. Larson , Jeffery Galloway , Siamak Tavallaei , Tim W. Majni , Robert Allan Lester , Anisha Anand , Eric Rose
发明人： Christian H. Post , George D. Megason , Brett D. Roscoe , Paul Santeler , John M. MacLaren , John E. Larson , Jeffery Galloway , Siamak Tavallaei , Tim W. Majni , Robert Allan Lester , Anisha Anand , Eric Rose
IPC分类号： G08B23/00
CPC分类号： G06F13/4081 , G06F13/409
摘要： A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.

10. 发明授权

US06975241B2 Removable memory cartridge system for use with a server or other processor-based device 有权
标题翻译：可移动内存盒系统，用于与服务器或其他基于处理器的设备配合使用
公开(公告)号：US06975241B2
公开(公告)日：2005-12-13
申请号：US10438150
申请日：2003-05-14
申请人： Christian H. Post , George D. Megason , Brett D. Roscoe , Paul Santeler , John M. MacLaren , John E. Larson , Jeffery Galloway , Siamak Tavallaei , Tim W. Majni , Robert Allan Lester , Anisha Anand , Eric Rose
发明人： Christian H. Post , George D. Megason , Brett D. Roscoe , Paul Santeler , John M. MacLaren , John E. Larson , Jeffery Galloway , Siamak Tavallaei , Tim W. Majni , Robert Allan Lester , Anisha Anand , Eric Rose
IPC分类号： G06F13/16 , G06F13/40 , G08B13/14 , G08B23/00
CPC分类号： G06F13/4081 , G06F13/409
摘要： A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.
摘要翻译：一种基于处理器的设备，其具有通过杠杆系统固定在底盘内的多个存储器盒。基于处理器的设备包括用于指示存储器系统操作条件的指示系统。当从基于处理器的设备移除存储器盒时，每个存储器盒具有保护组件以保护存储器盒内的存储器元件。基于处理器的设备是可操作的，使得可以从基于处理器的设备移除至少一个存储盒，而不影响基于处理器的设备的操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式