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1. 发明授权

US08675679B2 Cooperative writes over the address channel of a bus 有权
标题翻译：在总线的地址通道上进行合作写入
公开(公告)号：US08675679B2
公开(公告)日：2014-03-18
申请号：US13330734
申请日：2011-12-20
申请人： Richard Gerard Hofmann , Terence J. Lohman
发明人： Richard Gerard Hofmann , Terence J. Lohman
IPC分类号： H04J3/00
CPC分类号： G06F13/4243 , G06F13/42 , G06F13/4273
摘要： A method of communicating over a bus is disclosed. The bus includes a write address channel, a write channel, and a read address channel. The method includes sending an address from a sending device to a receiving device via the write address channel. The method further includes concurrently sending a portion of a payload to the receiving device via the write channel and another portion of the payload to the receiving device via the read address channel. When sending multiple sequential portions of the payload via the bus concurrently, the sending device is configured to give data ordering preference to the write channel over the read address channel by sending a first sequential portion of the multiple sequential portions via the write channel and sending a subsequent sequential portion of the multiple sequential portions via the read address channel.
摘要翻译：公开了一种通过总线进行通信的方法。总线包括写地址通道，写通道和读地址通道。该方法包括经由写入地址信道从发送设备发送地址到接收设备。该方法还包括经由读取地址信道经由写入信道和有效载荷的另一部分经由读取地址信道同时将一部分有效负载发送到接收设备。当经由总线同时发送有效负载的多个连续部分时，发送设备被配置为通过经由写入通道发送多个连续部分的第一顺序部分来通过读取地址信道给予写入信道的数据排序偏好，并且发送多个顺序部分的后续顺序部分经由读地址信道。

2. 发明授权

US08107492B2 Cooperative writes over the address channel of a bus 有权
标题翻译：在总线的地址通道上进行合作写入
公开(公告)号：US08107492B2
公开(公告)日：2012-01-31
申请号：US11468908
申请日：2006-08-31
申请人： Richard Gerard Hofmann , Terence J. Lohman
发明人： Richard Gerard Hofmann , Terence J. Lohman
IPC分类号： H04J3/00
CPC分类号： G06F13/4243 , G06F13/42 , G06F13/4273
摘要： A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to write a first portion of a payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.
摘要翻译：公开了一种用于通过总线在处理系统中通信的处理系统和方法。处理系统包括接收装置，具有第一，第二和第三信道的总线，以及配置成在第一信道上寻址接收装置并从第二信道上的接收装置读取有效载荷的发送装置，发送装置是还被配置为将所述有效负载的第一部分写入所述第一信道上的所述接收设备，并且将所述有效载荷的第二部分写入所述第三信道上的接收设备。

3. 发明申请

US20070233904A1 Auxiliary Writes Over Address Channel 有权
标题翻译：辅助写入地址通道
公开(公告)号：US20070233904A1
公开(公告)日：2007-10-04
申请号：US11468933
申请日：2006-08-31
申请人： Richard Gerard Hofmann , Terence J. Lohman
发明人： Richard Gerard Hofmann , Terence J. Lohman
IPC分类号： G06F3/00
CPC分类号： G06F13/4282 , G06F13/4265
摘要： A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to select between the first and third channels to write a payload to the receiving device.
摘要翻译：公开了一种用于通过总线在处理系统中通信的处理系统和方法。处理系统包括接收装置，具有第一，第二和第三信道的总线，以及配置成在第一信道上寻址接收装置并从第二信道上的接收装置读取有效载荷的发送装置，发送装置是还被配置为在所述第一和第三信道之间选择以将有效负载写入所述接收设备。

4. 发明授权

US5621897A Method and apparatus for arbitrating for a bus to enable split transaction bus protocols 失效
标题翻译：用于仲裁总线以实现拆分事务总线协议的方法和装置
公开(公告)号：US5621897A
公开(公告)日：1997-04-15
申请号：US421114
申请日：1995-04-13
申请人： Bechara F. Boury , Charles E. Kuhlmann , Terence J. Lohman , Neil W. Songer , Ronald E. Valli
发明人： Bechara F. Boury , Charles E. Kuhlmann , Terence J. Lohman , Neil W. Songer , Ronald E. Valli
IPC分类号： G06F13/362 , G06F13/36
CPC分类号： G06F13/362
摘要： An arrangement and method for arbitration to enable split transaction bus protocols provides for a slave to assert a mask signal that sets a mask bit in a mask register when the slave is not ready to complete a requested transaction. A requesting master is forced off the bus and prevented from re-arbitrating while the mask bit is set in the register. When the slave is ready to complete the transaction, a release master signal is asserted which causes the bit in the shift register to be reset. The requesting master is then able to re-arbitrate for use of the bus to complete the transaction. The usable bandwidth of the bus is increased since other masters are able to arbitrate and use the bus until the slave is ready to complete the transaction with the first requesting master.
摘要翻译：用于启用拆分事务总线协议的仲裁的布置和方法提供从机在从机未准备好完成所请求的事务时，提供设置掩码寄存器中的掩码位的掩码信号。请求主机被强制关闭总线，并防止在掩码位置位在寄存器中进行重新仲裁。当从机准备好完成交易时，断言主信号被断言，这使得移位寄存器中的位被复位。然后，请求主机能够重新仲裁以使用总线来完成交易。总线的可用带宽增加，因为其他主机能够仲裁和使用总线，直到从机准备完成与第一请求主机的交易。

5. 发明授权

US5333274A Error detection and recovery in a DMA controller 失效
标题翻译： DMA控制器中的错误检测和恢复
公开(公告)号：US5333274A
公开(公告)日：1994-07-26
申请号：US778040
申请日：1991-10-15
申请人： Nader Amini , Bechara F. Boury , Sherwood Brannon , Richard G. Hofmann , Terence J. Lohman
发明人： Nader Amini , Bechara F. Boury , Sherwood Brannon , Richard G. Hofmann , Terence J. Lohman
IPC分类号： G06F13/00 , G06F11/00 , G06F11/14 , G06F11/20 , G06F13/28
CPC分类号： G06F13/28 , G06F11/00 , G06F11/0751 , G06F11/0757 , G06F11/0763 , G06F11/1402
摘要： A DMA controller with error circuitry which detects DMA error conditions is disclosed. The error circuitry causes the DMA controller to perform completion tasks before terminating a DMA transfer, advantageously providing a DMA controller which may exit gracefully upon detection of an error condition with the potential of error recovery.
摘要翻译：公开了一种具有检测DMA错误状况的错误电路的DMA控制器。错误电路使得DMA控制器在终止DMA传输之前执行完成任务，有利地提供了一个DMA控制器，它可以在检测到具有错误恢复潜力的错误状况时正常地退出。

6. 发明申请

US20070204091A1 Single Bus Command for Transferring Data in a Processing System 有权
标题翻译：用于在处理系统中传输数据的单总线命令
公开(公告)号：US20070204091A1
公开(公告)日：2007-08-30
申请号：US11557119
申请日：2006-11-07
申请人： Richard Gerard Hofmann , Terence J. Lohman
发明人： Richard Gerard Hofmann , Terence J. Lohman
IPC分类号： G06F13/36
CPC分类号： G06F13/28 , G06F13/4022
摘要： A processing system and method for transferring data in a processing system. The processing system includes a bus mastering device, a plurality of slave devices, and a bus interconnect configured to switch the bus mastering device between the slave devices. Each of the slave devices has a plurality of addresses. The bus interconnect includes a DMA controller configured to transfer data from a first one of the addresses to a second one of the addresses in response to a single bus command from the bus mastering device.
摘要翻译：一种用于在处理系统中传送数据的处理系统和方法。处理系统包括总线主控装置，多个从设备和配置成在从设备之间切换总线主控装置的总线互连。每个从设备具有多个地址。总线互连包括DMA控制器，其被配置为响应于来自总线主控装置的单个总线命令，将数据从地址的第一个地址传送到第二个地址。

7. 发明授权

US5544346A System having a bus interface unit for overriding a normal arbitration scheme after a system resource device has already gained control of a bus 失效
标题翻译：系统具有总线接口单元，用于在系统资源设备已经获得总线控制之后超越正常的仲裁方案
公开(公告)号：US5544346A
公开(公告)日：1996-08-06
申请号：US353165
申请日：1994-12-09
申请人： Nader Amini , Bechara F. Boury , Sherwood Brannon , Richard L. Horne , Terence J. Lohman
发明人： Nader Amini , Bechara F. Boury , Sherwood Brannon , Richard L. Horne , Terence J. Lohman
IPC分类号： G06F13/36 , G06F13/16 , G06F13/00 , G06F13/40
CPC分类号： G06F13/1605
摘要： An information handling systems capable of transferring data among various system resource devices such as input/output (I/O) devices and a system memory includes a first bus coupled to the system memory, a second bus coupled to the system resource devices, and a bus interface unit (BIU) coupled between the first bus and the second bus. Each of the system resource devices is capable of controlling the second bus after arbitrating therefor. The BIU includes a buffer for temporary storage of data being transferred between the first bus and the second bus, and control logic for generating a lock control signal, after one of the system resource devices has gained control of the second bus by arbitration, to gain control of the first bus to prevent other system resource devices from accessing the first bus. The control signal is dynamically generated by the BIU based on programmable conditions relating to the data transfer, thus optimizing data transfers between the first bus and the second bus. The control signal may act as an override to the normal memory controller arbitration scheme to prioritize access of the system resource devices to the system memory.
摘要翻译：能够在诸如输入/输出（I / O）设备和系统存储器的各种系统资源设备之间传送数据的信息处理系统包括耦合到系统存储器的第一总线，耦合到系统资源设备的第二总线，以及总线接口单元（BIU），耦合在第一总线和第二总线之间。每个系统资源设备在对其进行仲裁之后能够控制第二总线。 BIU包括用于临时存储在第一总线和第二总线之间传输的数据的缓冲器，以及用于在系统资源设备之一通过仲裁获得第二总线的控制之后产生锁定控制信号的控制逻辑，以获得控制第一总线以防止其他系统资源设备访问第一总线。基于与数据传输相关的可编程条件，BIU动态地产生控制信号，从而优化第一总线与第二总线之间的数据传输。控制信号可以作为对正常存储器控制器仲裁方案的覆盖，以优先考虑系统资源设备对系统存储器的访问。

8. 发明授权

US08108563B2 Auxiliary writes over address channel 有权
标题翻译：辅助写入地址通道
公开(公告)号：US08108563B2
公开(公告)日：2012-01-31
申请号：US11468933
申请日：2006-08-31
申请人： Richard Gerard Hofmann , Terence J. Lohman
发明人： Richard Gerard Hofmann , Terence J. Lohman
IPC分类号： G06F3/00
CPC分类号： G06F13/4282 , G06F13/4265
摘要： A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to select between the first and third channels to write a payload to the receiving device.
摘要翻译：公开了一种用于通过总线在处理系统中通信的处理系统和方法。处理系统包括接收装置，具有第一，第二和第三信道的总线，以及配置成在第一信道上寻址接收装置并从第二信道上的接收装置读取有效载荷的发送装置，发送装置是还被配置为在所述第一和第三信道之间选择以将有效负载写入所述接收设备。

9. 发明授权

US07933289B2 Cooperative writes over the address channel of a bus 有权
公开(公告)号：US07933289B2
公开(公告)日：2011-04-26
申请号：US11468908
申请日：2006-08-31
申请人： Richard Gerard Hofmann , Terence J. Lohman
发明人： Richard Gerard Hofmann , Terence J. Lohman
IPC分类号： H04J3/00
摘要： A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to write a first portion of a payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.

10. 发明授权

US07249210B2 Bus access arbitration scheme 有权
标题翻译：总线访问仲裁方案
公开(公告)号：US07249210B2
公开(公告)日：2007-07-24
申请号：US11070338
申请日：2005-03-01
申请人： Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Terence J. Lohman
发明人： Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Terence J. Lohman
IPC分类号： G06F13/36 , G06F13/14 , G06F13/40
CPC分类号： G06F13/362
摘要： A bus arbitration scheme in a processing system. The processing system includes a bus, a plurality of processors coupled to the bus, and a bus arbiter. The bus arbiter may assign a first tier weight to each of the processors in a first tier, and a second tier weight to each of the processors in a second tier. The bus arbiter may sequentially grant bus access to the one or more processors during an initial portion of a bus interval based on the assigned second tier weights, and grant bus access to any one of the processors during the initial portion of the bus interval in response to a request from said any one of the processors having a first tier weight. When multiple processors are requesting access to the bus, the bus arbiter may grant bus access to the requesting processor with the highest weight in the highest tier.
摘要翻译：处理系统中的总线仲裁方案。处理系统包括总线，耦合到总线的多个处理器和总线仲裁器。总线仲裁器可以向第一层中的每个处理器分配第一层权重，并且向第二层中的每个处理器分配第二层权重。总线仲裁器可以基于所分配的第二层权重在总线间隔的初始部分期间顺序地授予对一个或多个处理器的总线访问，并且在总线间隔的初始部分中响应地授予总线对任何一个处理器的访问来自所述任何一个具有第一层权重的处理器的请求。当多个处理器请求访问总线时，总线仲裁器可以向最高级别中具有最高权重的请求处理器授予总线访问。

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