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1. 发明授权

US07548996B2 Data streamer 有权
标题翻译：数据流
公开(公告)号：US07548996B2
公开(公告)日：2009-06-16
申请号：US11224738
申请日：2005-09-12
申请人： David Baker , Christopher Basoglu , Benjamin Cutler , Gregorio Gervasio , Woobin Lee , Yatin Mundkur , Toru Nojiri , John O'Donnell , John Poole, legal representative , Ashok Raman , Eric Rehm , Radhika Thekkath
发明人： David Poole
IPC分类号： G06F13/28
CPC分类号： G06F13/30 , G06F13/1605
摘要： In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus.An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.
摘要翻译：在具有处理器，主存储器和多个I / O设备的多个模块的信息处理系统中，用于在处理器，主存储器和I / O设备之间执行数据传送操作的数据传送开关包括请求总线其具有用于从多个模块中的每一个接收读取和写入请求的请求总线仲裁器。处理器存储器总线被配置为从包括处理器的预定数量的模块接收地址和数据信息。处理器存储器总线具有用于从耦合到处理器存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。内部存储器总线被配置为从包括存储器和I / O设备的预定数量的模块接收地址和数据信息。内部存储器总线具有用于从耦合到内部存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。收发器系统耦合到处理器存储器总线和内部存储器总线，用于在处理器存储器总线和内部存储器总线之间传送数据。

2. 发明授权

US06434649B1 Data streamer 有权
标题翻译：数据流
公开(公告)号：US06434649B1
公开(公告)日：2002-08-13
申请号：US09173297
申请日：1998-10-14
申请人： David Baker , Christopher Basoglu , Benjamin Cutler , Gregorio Gervasio , Woobin Lee , Yatin Mundkur , Toru Nojiri , John O'Donnell , David Poole , Ashok Raman , Eric Rehm , Radhika Thekkath
发明人： David Baker , Christopher Basoglu , Benjamin Cutler , Gregorio Gervasio , Woobin Lee , Yatin Mundkur , Toru Nojiri , John O'Donnell , David Poole , Ashok Raman , Eric Rehm , Radhika Thekkath
IPC分类号： G06F1300
CPC分类号： G06F13/30 , G06F13/1605
摘要： In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.
摘要翻译：在具有处理器，主存储器和多个I / O设备的多个模块的信息处理系统中，用于在处理器，主存储器和I / O设备之间执行数据传送操作的数据传送开关包括请求总线其具有用于从多个模块中的每一个接收读取和写入请求的请求总线仲裁器。处理器存储器总线被配置为从包括处理器的预定数量的模块接收地址和数据信息。处理器存储器总线具有用于从耦合到处理器存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。内部存储器总线被配置为从预定数量接收地址和数据信息的模块，包括内存和I / O设备。内部存储器总线具有用于从耦合到内部存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。收发器系统耦合到处理器存储器总线和内部存储器总线，用于在处理器存储器总线和内部存储器总线之间传送数据。

3. 发明授权

US07051123B1 Data transfer engine of a processor having a plurality of modules 有权
标题翻译：具有多个模块的处理器的数据传输引擎
公开(公告)号：US07051123B1
公开(公告)日：2006-05-23
申请号：US09710192
申请日：2000-11-10
申请人： David Baker , Christopher Basoglu , Benjamin Cutler , Gregorio Gervasio , Woobin Lee , Yatin Mundkur , Toru Nojiri , John O'Donnell , Ashok Raman , Eric Rehm , Radhika Thekkath
发明人： David Baker , Christopher Basoglu , Benjamin Cutler , Gregorio Gervasio , Woobin Lee , Yatin Mundkur , Toru Nojiri , John O'Donnell , Ashok Raman , Eric Rehm , Radhika Thekkath
IPC分类号： G06F3/00
CPC分类号： G06F13/30 , G06F13/1605
摘要： In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus.An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.
摘要翻译：在具有处理器，主存储器和多个I / O设备的多个模块的信息处理系统中，用于在处理器，主存储器和I / O设备之间执行数据传送操作的数据传送开关包括请求总线其具有用于从多个模块中的每一个接收读取和写入请求的请求总线仲裁器。处理器存储器总线被配置为从包括处理器的预定数量的模块接收地址和数据信息。处理器存储器总线具有用于从耦合到处理器存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。内部存储器总线被配置为从包括存储器和I / O设备的预定数量的模块接收地址和数据信息。内部存储器总线具有用于从耦合到内部存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。收发器系统耦合到处理器存储器总线和内部存储器总线，用于在处理器存储器总线和内部存储器总线之间传送数据。

4. 发明申请

US20060288134A1 Data streamer 有权
公开(公告)号：US20060288134A1
公开(公告)日：2006-12-21
申请号：US11224738
申请日：2005-09-12
申请人： David Baker , Christopher Basoglu , Benjamin Cutler , Gregorio Gervasio , Woobin Lee , Yatin Mundkur , Toru Nojiri , John O'Donnell , David Poole , Ashok Raman , Eric Rehm , Radhika Thekkath , John Poole
发明人： David Baker , Christopher Basoglu , Benjamin Cutler , Gregorio Gervasio , Woobin Lee , Yatin Mundkur , Toru Nojiri , John O'Donnell , David Poole , Ashok Raman , Eric Rehm , Radhika Thekkath , John Poole
IPC分类号： G06F5/00
CPC分类号： G06F13/30 , G06F13/1605
摘要： In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.

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